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TLC2552ID Datasheet(PDF) 9 Page - Texas Instruments |
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TLC2552ID Datasheet(HTML) 9 Page - Texas Instruments |
9 / 23 page TLC2551, TLC2552, TLC2555 5 V, LOW POWER, 12-BIT, 400 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS276 –MARCH 2000 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range, VDD = VREF = 4.5 V to 5.5 V, SCLK frequency = 20 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage VDD = 5.5 V, IOH = –0.2 mA at 30 pF load 2.4 V VOL Low-level output voltage VDD = 5.5 V, IOL = 0.8 mA at 30 pF load 0.4 V IO Off-state output current VO = VDD CS VDD 1 2.5 µA IOZ (high-impedance-state) VO = 0 CS = VDD –1 –2.5 µA IIH High-level input current VI = VDD 0.005 2.5 µA IIL Low-level input current VI = 0 V –0.005 2.5 µA ICC Operating supply current CS at 0 V, VDD = 4.5 V ~ 5.5 V 3 3.5 mA ICC( O ) Autopower-down current (0.5 µs inactive) For all digital inputs, 0 ≤ VI ≤ 0 3VorVI ≥ VDD 03 V 8 µA ICC(AUTOPWDN) Autopower-down current (5 µs inactive) 0 ≤ VI ≤ 0.3 V or VI ≥ VDD– 0.3 V, SCLK = 0, VDD = 4.5 V to 5.5 V, Ext ref 1 µA Selected analog input channel leakage Selected channel at VDD 1 µA gg current Selected channel at 0 V –1 µA Ci Input capacitance Analog inputs 20 45 50 pF Ci Input capacitance Control Inputs 5 25 pF Input on resistance VDD = 5.5 V 500 Ω Delay time, delay from CS falling edge to SDO valid, td(CSL-SDOV) VDD = REF = 5.5 V, 30 pF 40 ns Delay time, delay from FS falling edge to SDO valid, td(FSL-SDOV) VDD = REF = 5.5 V, 30 pF 1 ns Delay time, delay from SCLK rising edge to SDO valid, td(SCLKH-SDOV) VDD = REF = 5.5 V, 30 pF 11 ns Delay time, delay from 17th SCLK rising edge to SDO 3-state, td(SCLK17H-SDOZ) VDD = REF = 5.5 V, 30 pF 30 ns tc Conversion time Conversion clock = internal oscillator 28 SCLK t(sample) Sampling time See Note 3 300 ns Autopower down Action time ICC start to decrease 0.5 SCLK Autopower down Wakeup time ICC down to MIN [ICC(AUTOPWDN)] 1 2 ms Autopower down 0.5 SCLK † All typical values are at VDD = 5 V, TA = 25°C. NOTE 3: Minimal t(sample) is given by 0.9 × 50 pF × (RS + 0.5 kΩ), where RS is the source output impedance. |
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