TLC2933

HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS136A – APRIL 1996 – REVISED JUNE 1997

5

POST OFFICE BOX 655303

recommended operating conditions

MIN

NOM

MAX

UNIT

Supply voltage VDD (each supply see Note 3)

VDD = 3 V

2.85

3

3.15

V

Supply voltage, VDD (each supply, see Note 3)

VDD = 5 V

4.75

5

5.25

V

Input voltage, VI (inputs except VCO IN)

0

VDD

V

Output current, IO (each output)

0

±2

mA

VCO control voltage at VCO IN

1

VDD

V

Lock frequency

VDD = 3 V

37

55

MHz

Lock frequency

VDD = 5 V

43

100

MHz

Bias resistor RBIAS

VDD = 3 V

1.8

2.7

k

Ω

Bias resistor, RBIAS

VDD = 5 V

2.2

3

k

Ω

NOTE 3: It is recommended that the logic supply terminal (LOGIC VDD) and the VCO supply terminal (VCO VDD) be at the same voltage and

separated from each other.

(unless otherwise noted)

VCO section

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOH

High-level output voltage

IOH = – 2 mA

2.4

V

VOL

Low-level output voltage

IOL = 2 mA

0.3

V

VIT +

Positive input threshold voltage at TEST, VCO INHIBIT

0.9

1.5

2.1

V

II

Input current at TEST, VCO INHIBIT

VI = VDD or ground

±1

µA

Zi(VCO IN)

Input impedance at VCO IN

VCO IN = 1/2 VDD

10

M

Ω

IDD(INH)

VCO supply current (inhibit)

See Note 4

0.01

1

µA

IDD(VCO)

VCO supply current

See Note 5

5.1

15

mA

NOTES:

4. The current into VCO VDD and LOGIC VDD when VCO INHIBIT = VDD and PFD INHIBIT is high.

5. The current into VCO VDD and LOGIC VDD when VCO IN = 1/2 VDD, RBIAS = 2.4 kΩ, VCO INHIBIT = ground, and PFD INHIBIT

is high.

PFD section

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOH

High-level output voltage

IOH = – 2 mA

2.7

V

VOL

Low-level output voltage

IOL = 2 mA

0.2

V

IOZ

High-impedance-state output current

PFD INHIBIT = high,

VI = VDD or ground

±1

µA

VIH

High-level input voltage at FIN–A, FIN–B

2.1

V

VIL

Low-level input voltage at FIN–A, FIN–B

0.9

V

VIT +

Positive input threshold voltage at PFD INHIBIT

0.9

1.5

2.1

V

Ci

Input capacitance at FIN–A, FIN–B

5

pF

Zi

Input impedance at FIN–A, FIN–B

10

M

Ω

IDD(Z)

High-impedance-state PFD supply current

See Note 6

0.01

1

µA

IDD(PFD)

PFD supply current

See Note 7

0.7

4

mA

NOTES:

6. The current into LOGIC VDD when FIN–A and FIN–B = ground, PFD INHIBIT = VDD, PFD OUT open, and VCO OUT is inhibited.

7. The current into LOGIC VDD when FIN–A and FIN–B = 30 MHz (VI(PP) = 3 V, rectangular wave), PFD INHIBIT = GND, PFD OUT

open, and VCO OUT is inhibited.