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TLC32045I Datasheet(PDF) 10 Page - Texas Instruments |
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TLC32045I Datasheet(HTML) 10 Page - Texas Instruments |
10 / 39 page TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I VOICE-BAND ANALOG INTERFACE CIRCUITS SLAS017F – MARCH 1988 – REVISED MAY 1995 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 explanation of internal timing configuration All of the internal timing of the AIC is derived from the high-frequency clock signal that drives the master clock input. The shift clock signal, which strobes the serial port data between the AIC and DSP, is derived by dividing the master clock input signal frequency by four. Low-pass: SCF Clock Frequency (D Aor A D path) + Master Clock Frequency 2 Contents of Counter A Conversion Frequency + SCF Clock Frequency (D AorA D path) Contents of Counter B High-pass: SCF Clock Frequency (A D Path) + A D Conversion Frequency Shift Clock Frequency + Master Clock Frequency 4 TX counter A and TX counter B, which are driven by the master clock, determine the D/A conversion timing. Similarly, RX counter A and RX counter B determine the A/D conversion timing. In order for the low-pass switched-capacitor filter in the D/A path to meet its transfer function specifications, the frequency of its clock input must be 288 kHz. If the clock frequency is not 288 kHz, the filter transfer function frequencies are frequency-scaled by the ratios of the clock frequency to 288 kHz. Thus, to obtain the specified filter response, the combination of master clock frequency and TX counter A and RX counter A values must yield a 288-kHz switched-capacitor clock signal. This 288-kHz clock signal can then be divided by the TX counter B to establish the D/A conversion timing. The transfer function of the bandpass switched-capacitor filter in the A/D path is a composite of its high-pass and low-pass section transfer functions. The high-frequency roll-off of the low-pass section meets the bandpass filter transfer function specification when the low-pass section SCF is 288 kHz. Otherwise, the high-frequency roll-off will be frequency-scaled by the ratio of the high-pass section’s SCF clock to 288 kHz. The low-frequency roll-off of the high-pass section meets the bandpass filter transfer function specification when the A/D conversion rate is 8 kHz. Otherwise, the low-frequency roll-off of the high-pass section is frequency-scaled by the ratio of the A/D conversion rate to 8 kHz. TX counter A and TX counter B are reloaded every D/A conversion period, while RX counter A and RX counter B are reloaded every A/D conversion period. The TX counter B and RX counter B are loaded with the values in the TB and RB registers, respectively. Via software control, the TX counter A can be loaded with either the TA register, the TA register less the TA’ register, or the TA register plus the TA’ register. By selecting the TA register less the TA’ register option, the upcoming conversion timing occurs earlier by an amount of time that equals TA’ times the signal period of the master clock. By selecting the TA register plus the TA’ register option, the upcoming conversion timing occurs later by an amount of time that equals TA’ times the signal period of the master clock. The D/A conversion timing can be advanced or retarded. An identical ability to alter the A/D conversion timing is provided. In this case, however, the RX counter A can be programmed via software control with the RA register, the RA register less the RA’ register, or the RA register plus the RA’ register. The ability to advance or retard conversion timing is particularly useful for modem applications. This feature allows controlled changes in the A/D and D/A conversion timing. This feature can be used to enhance signal-to-noise performance, to perform frequency-tracking functions, and to generate nonstandard modem frequencies. |
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