TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M

LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS

SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999

9

POST OFFICE BOX 655303

extended sampling, asynchronous start of sampling: CSTART operation

This allows the analog inputs of the device to be directly interfaced to a wide range of input source impedances.

The extended sampling mode consumes higher power depending on the duration of the sampling period

chosen.

CSTART controls the sampling period and starts the conversion. The falling edge of CSTART initiates the

sampling period of a preset channel. The low time of CSTART controls the acquisition time of the input

sample-and-hold circuit. The sample is held on the rising edge of CSTART. Asserting CSTART causes the

converter to perform a new sample of the signal on the preset valid MUX channel (one of the eight) and discard

the current conversion result ready for output. Sampling continues as long as CSTART is active (negative). The

rising edge of CSTART ends the sampling cycle. The conversion cycle starts two internal system clocks after

the rising edge of CSTART.

Once the conversion is complete, the processor can initiate a normal I/O cycle to read the conversion result and

set the MUX address for the next conversion. Since the internal flag AsyncFlag is set high, this flag setting

indicates the cycle is an output cycle, so no conversion is performed during the cycle. The internal state machine

tests the AsyncFlag on the falling edge of CS. AsyncFlag is set high at the rising edge of CSTART, and it is reset

low at the rising edge of each CS. A conversion cycle follows a sampling cycle only if AsyncFlag is tested as

low at the falling edge of CS. As shown in Figure 2, an asynchronous I/O cycle can be removed by two

consecutive normal I/O cycles.

Table 4. TLV1544/1548 Hardware Configuration for Different Operating Modes

OPERATING MODES

CS

CSTART

AsyncFlag at CS

↓

ACTION

Normal sampling

Low

High

Low

Fixed 6 I/O CLK sampling, synchronous conversion follows

Normal I/O (read out only)

Low

High

High

No sampling, no conversion

Extended sampling

High

Low

N/A

Flexible sampling period controlled by CSTART,

asynchronous conversion follows