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TLV320AC57DW Datasheet(PDF) 10 Page - Texas Instruments |
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TLV320AC57DW Datasheet(HTML) 10 Page - Texas Instruments |
10 / 23 page TLV320AC56, TLV320AC57 3-V VOICE-BAND AUDIO PROCESSORS (VBAP ™) SLWS044B – JUNE 1996 – REVISED OCTOBER 1997 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements clock timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1 through Figure 4) MIN NOM† MAX UNIT tt Transition time, CLK and DCLKX /DCLKR 10 ns Duty cycle, CLK 45% 50% 55% Duty cycle, DCLKX /DCLKR 45% 50% 55% † All nominal values are at VCC = 3 V, TA = 25°C. transmit timing requirements over recommended ranges of supply voltage and operating free-air temperature, fixed-data-rate mode (see Figure 2) MIN MAX UNIT tsu(FSX) Setup time, FSX high before CLK ↓ 20 468 ns th(FSX) Hold time, FSX high after CLK ↓ 20 468 ns receive timing requirements over recommended ranges of supply voltage and operating free-air temperature, fixed-data-rate mode (see Figure 1) MIN MAX UNIT tsu(FSR) Setup time, FSR high before CLK ↓ 20 468 ns th(FSR) Hold time, FSR high after CLK ↓ 20 468 ns tsu(DIN) Setup time, DIN high or low before CLK ↓ 20 ns th(DIN) Hold time, DIN high or low after CLK ↓ 20 ns transmit timing requirements over recommended ranges of supply voltage and operating free-air temperature, variable-data-rate mode (see Figure 4) MIN MAX UNIT tsu(FSX) Setup time, FSX high before DCLKX ↓ 40 tc(DCLKX)–40 ns th(FSX) Hold time, FSX high after DCLKX ↓ 35 tc(DCLKX)–35 ns receive timing requirements over recommended ranges of supply voltage and operating free-air temperature, variable-data-rate mode (see Figure 3) MIN MAX UNIT tsu(FSR) Setup time, FSR high before DCLKR ↓ 40 ns th(FSR) Hold time, FSR high after DCLKR ↓ 35 tc(DCLKR)–35 ns tsu(DIN) Setup time, DIN high or low before DCLKR ↓ 30 ns th(DIN) Hold time, DIN high or low after DCLKR ↓ 30 ns switching characteristics propagation delay times over recommended ranges of operating conditions, fixed-data-rate mode, CL = 0 to 10 pF (see Figure 2) PARAMETER TEST CONDITIONS MIN MAX UNIT tpd1 From CLK bit 1 high to DOUT bit 1 valid 35 ns tpd2 From CLK high to DOUT valid, bits 2 to n 35 ns tpd3 From CLK bit n low to DOUT bit n Hi-Z 30 ns tpd4 From CLK bit 1 high to TSX active (low) Rpullup = 1.24 kW 40 ns tpd5 From CLK bit n low to TSX inactive (high) Rpullup = 1.24 kΩ 30 ns |
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