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TLV320AIC27IPFB Datasheet(PDF) 7 Page - Texas Instruments |
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TLV320AIC27IPFB Datasheet(HTML) 7 Page - Texas Instruments |
7 / 52 page TLV320AIC27 STEREO AUDIO CODEC SLAS253 – MARCH 2000 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics, AVDD = 5 V, DVDD = 3.3 V, GND = 0 V, TA = 0°C to 70°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Digital Logic Levels (DVDD = 3.3 V or 5 V) VIL Input low level AVSS – 0.3 0.8 V VIH Input high level 2.2 AVDD + 0.3 V VOL Output low 0.1 × DVDD V VOH Output high 0.9 × DVDD V Analog I/O Levels (input signals on any inputs, outputs on LINEOUT L, R, and MONOOUT) Input level Minimum input impedance = 10 k Ω AVSS –100 mV AVDD +100 mV V Output level Into 10 k Ω load AVSS +100 mV Near rail to rail AVDD –100 mV V Reference Levels CAP2 Reference input/output 2/5 AVDD AVDD/2 3/5 AVDD V CAP2 impedance 75 k Ω VREF Mixer reference Buffered CAP2 V VREFOUT MIC reference Buffered CAP2 V CAP1 ADC reference Buffered CAP2 V AFILT1 DAC reference Buffered CAP2 V VREF current source (pins CAP1, AFILT2, VREF and VREFOUT) AVDD = 3 V 5 15 mA VREF current source (pins CAP1, AFILT1, VREF and VREFOUT) AVDD = 5 V 3 5 mA DAC Circuit Specifications (AVDD = 5 V) 48-kHz sampling SNR A-weighted (see Note 1) 85 95 dB Full-scale output voltage VREF = 2.5 V 1 Vrms THD –3-dB full-scale input 74 96 dB Frequency response 20 19 200 Hz Transition band 19 200 28 800 Hz Stop band 28 800 Hz Out of band rejection –40 dB Spurious-tone reduction –100 dB PSRR 20 Hz to 20 kHz 40 dB ADC Circuit Specifications (AVDD = 5 V) 48-kHz sampling SNR A-weighted (see Note 1) 75 90 dB ADC input for full-scale output VREF = 2.5 V 1 Vrms THD –6-dB voltage input 80 95 dB Frequency response 20 19 200 Hz Transition band 19 200 28 800 Hz Stop band 28 800 Hz Stop-band rejection –74 dB PSRR 20 Hz to 20 kHz 40 dB NOTE 1: SNR is the ratio of 0-dB signal output level to the output level with no signal, measured A-weighted over a 20 Hz to 20 kHz bandwidth. |
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