TLV5639C, TLV5639I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG

CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN

SLAS189 – MARCH 1999

6

POST OFFICE BOX 655303

analog output dynamic performance

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t (FS)

Output settling time full scale

RL = 10 kΩ,CL = 100 pF,

Fast

1

3

µs

ts(FS)

Output settling time, full scale

L

,

L

,

See Note 11

Slow

3.5

7

µs

t (CC)

Output settling time code to code

RL = 10 kΩ,CL = 100 pF,

Fast

0.5

1.5

µs

ts(CC)

Output settling time, code to code

L

,

L

,

See Note 12

Slow

1

2

µs

SR

Slew rate

RL = 10 kΩ,CL = 100 pF,

Fast

6

10

V/

µs

SR

Slew rate

L

,

L

,

See Note 13

Slow

1.2

1.7

V/

µs

Glitch energy

DIN = 0 to 1,

fCLK = 100 kHz,

CS = VDD

5

nV–S

SNR

Signal-to-noise ratio

73

78

SINAD

Signal-to-noise + distortion

fs = 480 kSPS, fout = 1 kHz,

fB 20 kHz

RL 10 kΩ

61

67

dB

THD

Total harmonic distortion

fB = 20 kHz,

RL = 10 kΩ,

CL = 100 pF

–69

–62

dB

SFDR

Spurious free dynamic range

CL = 100 F

63

74

NOTES: 11. Settling time is the time for the output signal to remain within

±0.5 LSB of the final measured value for a digital input code change

of 0x020 to 0xFDF or 0xFDF to 0x020.

12. Settling time is the time for the output signal to remain within

± 0.5 LSB of the final measured value for a digital input code change

of one count.

13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.

digital input timing requirements

MIN

NOM

MAX

UNIT

tsu(CS–WE)

Setup time, CS low before negative WE edge

15

ns

tsu(D)

Setup time, data ready before positive WE edge

10

ns

tsu(R)

Setup time, REG ready before positive WE edge

20

ns

th(DR)

Hold time, data and REG held valid after positive WE edge

5

ns

tsu(WE-LD)

Setup time, positive WE edge before LDAC low

5

ns

twH(WE)

Pulse duration, WE high

20

ns

tw(LD)

Pulse duration, LDAC low

23

ns