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TMS320BC52 Datasheet(PDF) 8 Page - Texas Instruments |
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TMS320BC52 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 91 page TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Pin Functions for the TMS320LC57 in the PBK Package (Continued) SIGNAL TYPE DESCRIPTION BUFFERED SERIAL PORT BDR I BSP receive data input BDX O/Z BSP transmit data output; in high-impedance state when not transmitting BCLKR I BSP receive-data clock input BCLKX I/O/Z BSP transmit-data clock; internal or external source BFSR I BSP receive frame-synchronization input BFSX I/O/Z BSP transmit frame-synchronization signal; internal or external source EMULATION/JTAG INTERFACE TDI I JTAG-test-port scan data input TDO O/Z JTAG-test-port scan data output TMS I JTAG-test-port mode select input TCK I JTAG-port clock input TRST I JTAG-port reset (with pull-down resistor). Disables JTAG when low EMU0 I/O/Z Emulation control 0. Reserved for emulation use EMU1 / OFF I/O/Z Emulation control 1. Puts outputs in high-impedance state when low CLOCK GENERATION AND CONTROL X1 O Oscillator output X2 / CLKIN I Clock input CLKMD1, CLKMD2, CLKMD3 I Clock-mode select inputs CLKOUT1 O/Z Device system-clock output POWER SUPPLY CONNECTIONS VDDA S Supply connection, address-bus output VDDD S Supply connection, data-bus output VDDC S Supply connection, control output VDDI S Supply connection, internal logic VSSA S Supply connection, address-bus output VSSD S Supply connection, data-bus output VSSC S Supply connection, control output VSSI S Supply connection, internal logic LEGEND: I = Input O = Output S = Supply Z = High impedance |
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Similar Description - TMS320BC52 |
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