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TMS3473 Datasheet(PDF) 1 Page - Texas Instruments |
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TMS3473 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 9 page TMS3473B PARALLEL DRIVER SOCS022B – NOVEMBER 1990 Copyright © 1990, Texas Instruments Incorporated 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 • TTL-Compatible Inputs • CCD-Compatible Outputs • Variable-Output Slew Rates With External Resistor Control • Full-Frame Operation • Frame-Transfer Operation • Solid-State Reliability • Adjustable Clock Levels description The TMS3473B is a monolithic CMOS integrated circuit designed to drive the parallel image-area gate (IAG), parallel storage-area gate (SAG), and antiblooming gate (ABG) inputs of the Texas Instruments (TI ™) virtual-phase CCD image sensors. The TMS3473B interfaces the CCD image sensor to a user-defined timing generator; it receives TTL-input signals from the timing generator and outputs level-shifted and slew-rate-adjusted signals to the image sensor. The TMS3473B allows operation of the CCD image sensor in either the interlace or noninterlace mode. When the TMS3473B I/N input is connected to VSS, the interlace mode is selected (see Figure 1); when I/N is connected to VCC, the noninterlace mode is selected (see Figure 2). ABOUT follows ABIN and switches between VABG+ and VABG–. IAOUT and SAOUT follow IAIN and SAIN, respectively, and switch between VCC and VSS. Additionally, ABOUT and IAOUT can each be made to output midlevel voltages. DC inputs to ABLVL and IALVL determine the midlevel voltages that can be output on ABOUT and IAOUT, respectively. A high-logic level on MIDSEL causes ABOUT to output its midlevel voltage; a low-logic level on MIDSEL causes IAOUT to output its midlevel voltage if the interlace mode is selected. Slew-rate adjustment of IAOUT and ABOUT is accomplished by connecting IASR to VCC and ABSR to VABG+ through external resistors. The larger the resistor values, the longer the rise and fall times are. A low-logic level on PD causes the TMS3473B to power down and all outputs to assume their low levels (IAOUT and SAOUT to VSS, ABOUT to VABG–). The TMS3473B is supplied in a 20-pin surface-mount package (DW) and is characterized for operation from –20 °C to 45°C. This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, precautions should be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 IALVL I/N IAIN ABIN MIDSEL SAIN PD GND VABG+ VSS VSS IASR ABSR VCC ABLVL IAOUT ABOUT SAOUT VCC VABG– DW PACKAGE (TOP VIEW) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TI is a trademark of Texas Instruments Incorporated. |
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