TMS44400, TMS44400P, TMS46400, TMS46400P

1048576-WORD BY 4-BIT

DYNAMIC RANDOM-ACCESS MEMORIES

SMHS562C – MAY 1995 – REVISED NOVEMBER 1996

4

POST OFFICE BOX 1443

refresh

A refresh operation must be performed at least once every 16 ms (128 ms for TMS4x400P) to retain data. This

can be achieved by strobing each of the 1024 rows (A0 – A9). A normal read or write cycle refreshes all bits in

each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level,

conserving power as the output buffer remains in the high-impedance state. Externally generated addresses

must be used for a RAS-only refresh. Hidden refresh can be performed while maintaining valid data at the

precharge period, similar to a RAS-only refresh cycle. The external address is ignored during the hidden-refresh

cycle.

CAS-before-RAS (CBR) refresh

external address is ignored and the refresh address is generated internally.

A low-power battery-backup refresh mode that requires less than 300-

µA (TMS46400P) or 500-µA

(TMS44400P) refresh current is available on the low-power devices. Data integrity is maintained using CBR

refresh with a period of 125

µs while holding RAS low for less than 1 µs. To minimize current consumption, all

self refresh

The self-refresh mode is entered by dropping CAS low prior to RAS going low. CAS and RAS are both held low

for a minimum of 100

µs. The chip is then refreshed by an on-board oscillator. No external address is required

since the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS and CAS

addresses) must be executed before continuing with normal operation, to ensure that the DRAM is fully

refreshed.

power up

To achieve proper device operation, an initial pause of 200

µs followed by a minimum of eight initialization cycles

( RAS-only or CBR) cycle.

test mode

The test mode is initiated with a CBR refresh cycle while simultaneously holding W low (WCBR). The entry cycle

performs an internal refresh cycle while internally setting the device to perform parallel read or write on

subsequent cycles. While in test mode, any desired data sequence can be performed on the device. The device

exits test mode if a CBR refresh cycle with W held high or a RAS-only refresh (ROR) cycle is performed.

The TMS4x400 / P is configured as a 512K

× 8 bit device in test mode, where each DQ pin has a separate 2-bit

parallel read- and write-data bus. During a read cycle, the two internal bits are compared for each DQ pin

separately. If the two bits agree, the DQ pin goes high; if not, the DQ pin goes low. The two bits are written to

reflect the state of their respective DQ pins during a parallel-write operation. Each DQ pin is independent of the

others, and any data pattern desired can be written on each DQ pin. Test time is reduced by a factor of 4 for

this series.