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TMS370C156A Datasheet(PDF) 3 Page - Texas Instruments |
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TMS370C156A Datasheet(HTML) 3 Page - Texas Instruments |
3 / 77 page TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 3 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Pin Descriptions (Continued) PIN † ‡ NAME ALTERNATE FUNCTION SDIP (64) LCC (68) I/O† DESCRIPTION‡ VSS1 8, 58,40 9 Ground reference for digital logic VSS2 — 16,62 Ground reference for digital I / O logic FUNCTION Single-chip mode: Port D is a general-purpose bidirectional I / O port. Each of the port D pins can be individually configured as a general-purpose I / O pin, primary memory control signal (function A) or secondary memory control A B primary memory control signal (function A), or secondary memory control signal (function B). All chip selects are independent and can be used for memory bank switching. Refer to Table 1 for function A memory accesses. D0 CSE2 OCF 59 64 I / O pin A: Chip select eighth output 2 goes low during memory accesses I / O pin B: Opcode fetch goes low during the opcode fetch memory cycle. D1 CSH3 — 56 60 I / O pin A: Chip select half output 3 goes low during memory accesses. I / O pin B: Reserved D2 CSH2 — — 59 I / O pin A: Chip select half output 2 goes low during memory accesses. I / O pin B: Reserved D3 SYSCLK SYSCLK 55 58 I / O pin A, B: Internal clock signal is 1 / 1 (PLL) or 1 / 4 XTAL2 / CLKIN frequency. D4 R/W R/W 54 57 I/O I / O pin A, B: Read / write output pin D5 CSPF — — 56 I/O I / O pin A: Chip select peripheral output for peripheral file goes low during memory accesses. I / O pin B: Reserved D6 CSH1 EDS 53 55 I / O pin A: Chip select half output 1 goes low during memory accesses. I / O pin B: External data strobe output goes low during memory accesses from external memory and has the same timings as the five chip selects. D7 CSE1 WAIT 52 54 I / O pin A: Chip select eighth output goes low during memory accesses. I / O pin B: Wait input pin extends bus signals. SCITXD SCIRXD SCICLK SCIIO1 SCIIO2 SCIIO3 28 27 26 30 29 28 I/O SCI transmit data output pin / general-purpose bidirectional pin (see Note 1) SCI receive data input pin / general-purpose bidirectional pin SCI bidirectional serial clock pin / general-purpose bidirectional pin T1IC / CR T1PWM T1EVT T1IO1 T1IO2 T1IO3 44 43 41 46 45 44 I/O Timer1 input capture / counter reset input pin / general-purpose bidirectional pin Timer1 pulse-width-modulation (PWM) output pin / general-purpose bidirectional pin Timer1 external event input pin / general-purpose bidirectional pin T2AIC1 / CR T2AIC2 / PWM T2AEVT T2AIO1 T2AIO2 T2AIO3 25 24 23 27 26 25 I/O Timer2A input capture 1 / counter reset input pin / general-purpose bidirectional pin Timer2A input capture 2 / PWM output pin / general-purpose bidirectional pin Timer2A external event input pin / general-purpose bidirectional pin SPISOMI SPISIMO SPICLK SPIIO1 SPIIO2 SPIIO3 47 46 45 49 48 47 I/O SPI slave output pin, master input pin / general-purpose bidirectional pin SPI slave input pin, master output pin / general-purpose bidirectional pin SPI bidirectional serial clock pin / general-purpose bidirectional pin † I = input, O = output ‡ Ports A, B, C, and D can be configured only as general-purpose I/O pins. Port D3 also can be configured as SYSCLK. NOTE 1: The three-pin configuration SCI is referred to as SCI1. Table 1. Function A: Memory Accesses Locations for ‘x5x Devices FUNCTION A ‘X50, ‘X52, ‘X53, AND ‘X56 ‘X58 ‘X59 CSEx 2000h – 3FFFh (8K bytes) A000h – BFFFh (8K bytes) E000h – EFFFh (4K bytes) CSHx 8000h – FFFFh (32K bytes) C000h – FFFFh (16K bytes) F000h – FFFFh (4K bytes) CSPF 10C0h – 10FFh (64 bytes) 10C0h – 10FFh (64 bytes) 10C0h – 10FFh (64 bytes) |
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