November 2006

ASM2I99456

rev 0.3

3.3V/2.5V LVCMOS Clock Fanout Buffer

5 of 14

Notice: The information in this document is subject to change without notice.

1

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

Input Frequency

0

250

2

MHz

÷1 output

0

250

2

MHz

FSELx=0

Maximum Output

Frequency

÷2 output

0

125

MHz

FSELx=1

Peak-to-peak input voltage

PCLK

500

1000

mV

LVPECL

3

Common Mode Range

PCLK

1.3

VCC-

0.8

V

LVPECL

Reference Input Pulse Width

1.4

nS

PCLK Input Rise/Fall Time

1.0

4

nS

0.8 to 2.0V

CCLK to any Q

2.2

2.8

4.45

nS

Propagation delay

CCLK to any Q

2.2

2.8

4.2

nS

Output Disable Time

10

nS

Output Enable Time

10

nS

Within one bank

150

pS

Any output bank, same output

divider

200

pS

Output-to-output

Skew

Any output, Any output divider

350

pS

Device-to-device Skew

2.25

nS

Output pulse skew

5

200

pS

÷1 output

47

50

53

%

Output Duty Cycle

÷2 output

45

50

55

%

Output Rise/Fall Time

0.1

1.0

nS

0.55 to 2.4V

2 The ASM2I99456 is functional up to an input and output clock frequency of 350MHz and is characterized up to 250 MHz.

4 Violation of the 1.0nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width,

output duty cycle and maximum frequency specifications.

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

Input high voltage

1.7

V

LVCMOS

Input low voltage

-0.3

0.7

V

LVCMOS

Peak-to-peak Input voltage

PCLK

250

mV

LVPECL

1

Common Mode Range

PCLK

1.1

V

LVPECL

Output High Voltage

1.8

V

2

Output Low Voltage

0.6

V

Output impedance

17 - 20

2

Ω

Input current

3

±200

µA

4

Maximum Quiescent Supply Current

2.0

mA

All VCC Pins

2 The ASM2I99456 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated

3 Input pull-up / pull-down resistors influence input current.