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ASM2I99456 Datasheet(PDF) 8 Page - PulseCore Semiconductor |
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ASM2I99456 Datasheet(HTML) 8 Page - PulseCore Semiconductor |
8 / 14 page November 2006 ASM2I99456 rev 0.3 3.3V/2.5V LVCMOS Clock Fanout Buffer 8 of 14 Notice: The information in this document is subject to change without notice. Figure 3. Optimized Dual Line Termination VCC VCC ÷2 GND DC (tP ÷T0 Χ 100%) tP T0 The time from the output controlled edge to the non-controlled edge, divided by the time output controlled edge, expressed as a percentage. tR VCC = 3.3V VCC = 2.5V 2.4 1.8V 0.55 0.6V tF Figure 5. Output Transition Time Test Reference PCLK PCLK QX VPP VCMR VCC VCC ÷2 GND tP(LH) tP(HL) Figure 6. Propagation Delay (tPD) Test Reference Figure 7. Output Duty Cycle (DC) tSK(LH) tSK(HL) VOH VCC ÷2 GND VCC VCC ÷2 GND The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 8. Output-to- Output Skew tSK(O) tR VCC = 3.3V VCC = 2.5V 2.4 1.8V 0.55 0.6V tF Figure 9. Output Transition Time Test Reference Differential Pulse Generator Z=50 Ω Z0=50Ω RT=50Ω VCC – 2V VTT RT=50Ω Figure 4. PCLK ASM2I99456 AC Test Reference for VCC = 3.3V and VCC = 2.5V Z0=50Ω ASM2I99456 DUT |
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