November 2006

ASM2P5T9070A

rev 0.2

Notice: The information in this document is subject to change without notice.

PulseCore Semiconductor Corporation

1715 S. Bascom Ave Suite 200, Campbell, CA 95008

• Tel: 408-879-9077 • Fax: 408-879-9018

www.pulsecoresemi.com

2.5V Single Data Rate 1:10 Clock Buffer Terabuffer

Features

•

Optimized for 2.5V LVTTL

•

Guaranteed Low Skew < 25pS (max)

•

Very low duty cycle distortion < 300pS (max)

•

High speed propagation delay < 2nS. (max)

•

Up to 200MHz operation

•

Very low CMOS power levels

•

Hot Insertable and over-voltage tolerant inputs

•

1:10 fanout buffer

•

2.5V Supply Voltage

•

Available in TSSOP Package

Functional Description

The ASM2P5T9070A 2.5V single data rate (SDR) clock

buffer is a single-ended input to ten single-ended outputs

buffer built on advanced metal CMOS technology. The

SDR clock buffer fanout from a single input to ten single-

ended outputs reduces the loading on the preceding driver

and provides an efficient clock distribution network.

The ASM2P5T9070A has two output banks that can be

asynchronously enabled/disabled. Multiple power and

grounds reduce noise.

Applications:

ASM2P5T9070A is targeted towards Clock and signal

distribution applications.

Block Diagram

GL

G1

A

Q1

Q2

Q3

Q4

Q5

OUTPUT

CONTROL

Q6

Q7

Q8

Q9

G2

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL

Q10