May 2007

ASM3P622S01B/J

rev 0.4

Low Frequency Timing-Safe™ Peak EMI Reduction IC

5 of 12

Notice: The information in this document is subject to change without notice.

Switching Characteristics for ASM3P622S01B/J

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

Output Frequency

30pF load

4

20

MHz

Duty Cycle

40

50

60

%

Output Rise Time

1, 2

Measured between 0.8V and 2.0V

2.5

nS

Output Fall Time

1, 2

Measured between 2.0V and 0.8V

2.5

nS

Output-to-output skew

2

All outputs equally loaded

250

pS

Delay, CLKIN Rising Edge to

CLKOUT Rising Edge

2

±250

pS

Device-to-Device Skew

2

of the device

700

pS

Cycle-to-cycle jitter

2

Loaded outputs

200

pS

PLL Lock Time

2

Stable power supply, valid clock presented

on CLKIN pin

1.0

mS

Note: 1. The parameters specified with loaded outputs.

2. Parameter is guaranteed by design and characterization. Not 100% tested in production