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ASM3P622S00EG-16-SR Datasheet(PDF) 6 Page - PulseCore Semiconductor |
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ASM3P622S00EG-16-SR Datasheet(HTML) 6 Page - PulseCore Semiconductor |
6 / 16 page May 2007 ASM3P622S00A/B/J/E/K rev 0.4 Low Frequency Timing-Safe™ Peak EMI Reduction IC 6 of 16 Notice: The information in this document is subject to change without notice. Operating Conditions for ASM3P622S00A/B/J/E/K Devices Parameter Description Min Max Unit VDD Supply Voltage 3.0 3.6 V TA Operating Temperature (Ambient Temperature) -40 +85 °C CL Load Capacitance 30 pF CIN Input Capacitance 7 pF Electrical Characteristics for ASM3P622S00A/B/J/E/K Parameter Description Test Conditions Min Typ Max Unit VIL Input LOW Voltage 1 0.8 V VIH Input HIGH Voltage 1 2.0 V IIL Input LOW Current VIN = 0V 50 µA IIH Input HIGH Current VIN = VDD 100 µA VOL Output LOW Voltage 2 IOL = 8mA 0.4 V VOH Output HIGH Voltage 2 IOH = -8mA 2.4 V IDD Supply Current Unloaded outputs 15 mA Zo Output Impedance 23 Ω Note: 1. CLKIN input has a threshold voltage of VDD/2 2. Parameter is guaranteed by design and characterization. Not 100% tested in production Switching Characteristics for ASM3P622S00A/B/J/E/K 1 Parameter Description Test Conditions Min Typ Max Unit 1/t1 Output Frequency 30pF load 4 20 MHz Duty Cycle 2 = (t2 / t1) * 100 Measured at VDD/2 40 50 60 % t3 Output Rise Time 2 Measured between 0.8V and 2.0V 2.5 nS t4 Output Fall Time 2 Measured between 2.0V and 0.8V 2.5 nS t5 Output-to-output skew 2 All outputs equally loaded 250 pS t6 Delay, CLKIN Rising Edge to CLKOUT Rising Edge 2 Measured at VDD /2 ±350 pS t7 Device-to-Device Skew 2 Measured at VDD/2 on the CLKOUT pins of the device 700 pS tJ Cycle-to-cycle jitter 2 Loaded outputs 200 pS tLOCK PLL Lock Time 2 Stable power supply, valid clock presented on CLKIN pin 1.0 mS Note: 1. All parameters specified with loaded outputs. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production |
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