September 2006

PCS2I99446

rev 0.5

2.5V and 3.3V LVCMOS Clock Distribution Buffer

6 of 14

Notice: The information in this document is subject to change without notice.

1,2

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

Input Frequency

0

250

3

MHz

÷1 output

0

250

2

MHz

FSELx=0

Maximum Output Frequency

÷2 output

0

125

MHz

FSELx=1

Reference Input Pulse Width

1.4

nS

CCLK Input Rise/Fall Time

1.0

4

nS

0.7 to 1.7V

CCLK0,1 to any Q

2.6

5.6

nS

Propagation delay

CCLK0,1 to any Q

2.6

5.5

nS

Output Disable Time

10

nS

Output Enable Time

10

nS

Within one bank

150

pS

Any output Bank,

Same output divider

200

pS

Output-to-output Skew

Any output, Any output

divider

350

pS

Device-to-device Skew

3.0

nS

Output pulse skew

5

200

pS

Output Duty Cycle

÷1 or ÷2 output

45

50

55

%

Output Rise/Fall Time

0.1

1.0

nS

0.6 to 1.8V

2 AC specifications are design targets, final specification is pending device characterization.

3 The PCS2I99446 is functional up to an input and output clock frequency of 350MHz and is characterized up to 250MHz.

4 Violation of the 1.0nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width,

output duty cycle and maximum frequency specifications.

1,2

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

Within one bank

150

pS

Any output Bank, Same output divider

250

pS

Output-to-output

Skew

Any output, Any output divider

350

pS

Device-to-device Skew

2.5

nS

Propagation delay

CCLK0,1 to any Q

See 3.3V table

Output pulse skew

3

250

pS

Output Duty Cycle

÷1 or ÷2 output

45

50

55

%

2 For all other AC specifications, refer to 2.5V or 3.3V tables according to the supply voltage of the output bank.