September 2006

PCS2I99446

rev 0.5

2.5V and 3.3V LVCMOS Clock Distribution Buffer

8 of 14

Notice: The information in this document is subject to change without notice.

Pulse

Generator

Z=50

Ω

PCS2I99446

2.4

1.8V

0.55

0.6V

Figure 5. Output Transition Time Test Reference

GND

GND

The pin-to-pin skew is defined as the worst case

difference in propagation delay between any similar

delay path within a single device

CCLK

GND

GND

CCLK

GND

GND

The time from the PLL controlled edge to the

non-controlled edge, divided by the time

between PLL controlled edges, expressed as a

percentage.

GND

The variation in cycle time of a signal between adjacent

cycles, over a random sample of adjacent cycle pairs

Figure 10. Cycle–to–Cycle Jitter