September 2006

PCS2I9940L

rev 1.1

Low Voltage 1:18 Clock Distribution Chip

7 of 13

Notice: The information in this document is subject to change without notice.

GND

PECL_CLK

Q

PECL_CLK

GND

LVCMOS_CLK

Q

GND

The time from the PLL controlled edge to the

non-controlled edge, divided by the time

between PLL controlled edges, expressed as a

percentage.

GND

Figure 5. Output Duty Cycle (DC)

GND

GND

The pin-to-pin skew is defined as the worst case

difference in propagation delay between any similar

delay path within a single device

2.4

1.8V

0.55

0.6V

Figure 7. Output Transition Time Test Reference

2.0

1.7V

0.8

0.7V

Figure 8. Input Transition Time Test Reference

Pulse

Generator

Z=50

Ω

PCS2I9940L

Differential

Pulse Generator

Z=50

Ω

PCS2I9940L