September 2006

PCS2I99448

rev 0.4

3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer

8 of 15

Notice: The information in this document is subject to change without notice.

multiple lines, the situation in Figure 4 “Optimized Dual

Line Termination” should be used. In this case, the series

terminating resistors are reduced such that when the

parallel combination is added to the output buffer

impedance the line impedance is perfectly matched.

17

Ω + 16Ω || 16Ω = 50Ω || 50Ω

25

Ω = 25Ω

Figure 4. Optimized Dual Line Termination

Power Consumption of the PCS299448 and

Thermal Management

The PCS2I99448 AC specification is guaranteed for the

entire operating frequency range up to 350MHz. The

PCS2I99448 power consumption and the associated

long-term

reliability

may

decrease

the

maximum

frequency limit, depending on operating conditions such

as clock frequency, supply voltage, output loading,

ambient temperature, vertical convection and thermal

conductivity of package and board. This section

describes the impact of these parameters on the junction

temperature and gives a guideline to estimate the

PCS2I99448 die junction temperature and the associated

device reliability.

Table 9. Die junction temperature and MTBF

Junction temperature (°C)

MTBF (Years)

100

20.4

110

9.1

120

4.2

130

2.0

Increased power consumption will increase the die

junction temperature and impact the device reliability

(MTBF). According to the system-defined tolerable

MTBF, the die junction temperature of the PCS2I99448

needs to be controlled and the thermal impedance of the

board/package should be optimized.The power dissipated

in the PCS2I99448 is represented in equation 1.

Where ICCQ is the static current consumption of the

PCS2I99448, CPD is the power dissipation capacitance

per output,

output load, N is the number of active outputs (N is

always 12 in case of the PCS2I99448). The PCS2I99448

supports driving transmission lines to maintain high signal

integrity and tight timing parameters. Any transmission

line will hide the lumped capacitive load at the end of the

board trace, therefore,

transmission line systems and can be eliminated from

equation 1. Using parallel termination output termination

results in equation 2 for power dissipation.

In equation 2, P stands for the number of outputs with a

parallel or thevenin termination, VOL, IOL, VOH and IOH

are a function of the output termination technique and

DCQ is the clock signal duty cycle. If transmission lines

are used

eliminated. In general, the use of controlled transmission

line techniques eliminates the impact of the lumped

capacitive loads at the end lines and greatly reduces the

power dissipation of the device. Equation 3 describes the

die junction temperature TJ as a function of the power

consumption.

(junction to ambient) and TA is the ambient temperature.

According to Table 9, the junction temperature can be

used to estimate the long-term device reliability. Further,

combining equation 1 and equation 2 results in a

maximum operating frequency for the PCS2I99448 in a

series terminated transmission line system, equation 4.

()

()

[]

()

4

1

3

2

1

1

2

Equation

V

I

R

T

T

V

N

C

f

Equation

R

P

T

T

Equation

V

I

DC

V

V

I

DC

C

C

N

f

V

I

V

P

Equation

V

C

C

N

f

V

I

P

CC

CCQ

thja

A

JMAX

CC

PD

CLOCKMAX

thja

TOT

A

J

P

OL

OL

Q

OH

CC

OH

Q

M

L

PD

CLOCK

CC

CCQ

CC

TOT

CC

M

L

PD

CLOCK

CC

CCQ

TOT

















⋅

−

−

⋅

⋅

⋅

=

⋅

+

=

⋅

⋅

−

+

−

⋅

+

























+

⋅

⋅

⋅

+

⋅

=

⋅

























+

⋅

⋅

⋅

+

=

∑

∑

∑

PCS2I99448

OUTPUT BUFFER

17Ω