September 2006

PCS2P20805A

rev 0.3

Notice: The information in this document is subject to change without notice.

PulseCore Semiconductor Corporation

1715 S. Bascom Ave Suite 200 Campbell, CA 95008

• Tel: 408-879-9077 • Fax: 408-879-9018

www.pulsecoresemi.com

2.5V CMOS Dual 1-To-5 Clock Driver

Features

•

Advanced CMOS Technology

•

Guaranteed low skew < 200pS (max.)

•

Very low propagation delay < 2.5nS (max)

•

Very low duty cycle distortion < 270pS (max)

•

Very low CMOS power levels

•

Operating frequency up to 166MHz

•

TTL compatible inputs and outputs

•

Two independent output banks with 3-state control

•

1:5 fanout per bank

•

"Heartbeat" monitor output

•

•

Available in SSOP and QSOP packages

Block Diagram

Functional Description

The PCS2P20805A is a 2.5V Clock driver built using

advanced CMOS technology. The device consists of two

banks of drivers, each with a 1:5 fanout and its own output

enable control. The device has a "heartbeat" monitor for

diagnostics and PLL driving. The MON output is identical to

all other outputs and complies with the output specifications

in

this

document.

The

PCS2P20805A

offers

low

capacitance inputs. The PCS2P20805A is designed for

high speed clock distribution where signal quality and skew

are critical. The PCS2P20805A also allows single point-to-

point transmission line driving in applications such as

address distribution, where one signal must be distributed

to multiple receivers with low skew and high signal quality.

Pin Diagram

MON

5

5

SSOP/ QSOP PACKAGE

TOP VIEW

MON

PCS2P20805A

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20