PCS2I3805AG-20-DR datasheet(7/12 Pages) PULSECORE

Part #	PCS2I3805AG-20-DR

Description	3.3V CMOS Buffer Clock Driver

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Manufacturer	PULSECORE [PulseCore Semiconductor]

Direct Link	http://www.onsemi.com/

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7 / 12 page

September 2006

PCS2P3805A

rev 0.3

3.3V CMOS Buffer Clock Driver

7 of 12

Notice: The information in this document is subject to change without notice.

Test Circuits and Waveforms

Switch Position

Test

Switch

Disable Low

Enable Low

6V

Disable High

Enable High

GND

Definitions:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse

Generator.

INPUT

tPLH1

tPHL1

3V

VOH

1.5V

VOL

OUTPUT 1

tSK(O) = | tPLH2 - tPLH1 | or | tPHL2 - tPHL1 |

tSK(O)

tPLH2

tPHL2

VOH

OUTPUT 2

Output Skew – tSK(o)

INPUT

OUTPUT

0V

tPLH

tPHL

1.5V

3V

VOH

2.0V

1.5V

0.8V

VOL

tF

tR

Package Delay

INPUT

0V

tPLH

tPHL

1.5V

3V

VOH

1.5V

VOL

OUTPUT

Pulse Skew

tSK(P) = | tPLH - tPLH |

Enable and Disable Times

ENABLE

tPLZ

3V

1.5V

0V

DISABLE

VOH

VOL

0V

0.3V

3.5V

0.3V

tPZL

0V

1.5V

3.5V

1.5V

SWITCH

CLOSED

tPZH

tPHZ

SWITCH

OPEN

CONTROL

INPUT

OUTPUT

NORMALLY

LOW

OUTPUT

NORMALLY

HIGH

Note:

Diagram shown for input Control Enable-LOW and input Control Disable-HIGH

Note:

Pulse Generator for all Pulses:f ≤ 10MHz; tF ≤ 2.5nS; tR ≤ 2.5nS

INPUT

0V

tPLH1

tPHL1

1.5V

3V

VOH

1.5V

VOL

Package 1

OUTPUT

tSK(t) = | tPLH2 - tPLH1 | or | tPHL2 - tPHL1 |

tSK(t)

tPLH2

tPHL2

VOH

1.5V

VOL

Package 2

OUTPUT

Package Skew – tSK(t)

VCC

RT

Pulse

Generator

VIN

D.U.T

50pF

GND

6V

500Ω

VOUT

Test Circuits for All Outputs

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