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PCS3P73Z01AWG-08-CR Datasheet(PDF) 4 Page - PulseCore Semiconductor |
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PCS3P73Z01AWG-08-CR Datasheet(HTML) 4 Page - PulseCore Semiconductor |
4 / 13 page May 2008 PCS3P73Z01AW rev 0.3 Wide Frequency range Timing-Safe™ Peak EMI reduction IC 4 of 13 Notice: The information in this document is subject to change without notice. Switching Characteristics for 2.5V Parameter Test Conditions Min Typ Max Unit FS=0 2 6 Input Frequency FS=1 6 16 FS=0 2 6 ModOUT FS=1 6 16 MHz Duty Cycle 1, 2 Measured at VDD /2 45 50 55 % Rise Time 1, 2 Measured between 20% to 80% 1.7 nS Fall Time 1, 2 Measured between 80% to 20% 0.9 nS FS=0; @ 5 MHz ±225 Cycle-to-Cycle Jitter 2 Unloaded outputs FS=1; @ 15 MHz ±150 pS FS=0; @ 6 MHz 175 Input-to-Output propagation Delay 2 Unloaded outputs with SSEXTR pin OPEN, No load on DLY_CTRL FS=1; @ 12 MHz 75 pS PLL Lock Time 2 Stable power supply, valid clock presented on CLKIN pin 3 mS Notes: 1. All parameters are specified with 10 pF loaded outputs 2. Parameter is guaranteed by design and characterization. Not 100% tested in production Switching Characteristics for 3.3V Parameter Test Conditions Min Typ Max Unit FS=0 2 6 Input Frequency FS=1 6 20 FS=0 2 6 ModOUT FS=1 6 20 MHz Duty Cycle 3,4 Measured at VDD /2 45 50 55 % Rise Time 3,4 Measured between 20% to 80% 1.2 nS Fall Time 3,4 Measured between 80% to 20% 0.8 nS FS=0; @ 5 MHz ±200 Cycle-to-Cycle Jitter 4 Unloaded outputs FS=1; @ 15 MHz ±125 pS FS=0; @ 6 MHz -75 Input-to-Output propagation Delay 4 Unloaded outputs with SSEXTR pin OPEN, No load on DLY_CTRL FS=1; @ 12 MHz 125 pS PLL Lock Time 4 Stable power supply, valid clock presented on CLKIN pin 3 mS Notes: 3. All parameters are specified with 10 pF loaded outputs 4. Parameter is guaranteed by design and characterization. Not 100% tested in production |
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