PCS3P623Z05A/B

May 2008

PCS3P623Z09A/B

rev 0.1

Notice: The information in this document is subject to change without notice.

PulseCore Semiconductor Corporation

1715 S. Bascom Ave Suite 200 Campbell, CA 95008

• Tel: 408-879-9077 • Fax: 408-879-9018

www.pulsecoresemi.com

Timing-Safe™ Peak EMI reduction IC

General Features

•

Clock distribution with Timing-Safe™ Peak EMI

Reduction

•

Input frequency range: 20MHz - 50MHz

•

Multiple low skew Timing-safe™ Outputs:

PCS3P623Z05: 5 Outputs

PCS3P623Z09: 9 Outputs

•

External Input-Output Delay Control option

•

Supply Voltage: 3.3V±0.3V

•

Commercial and Industrial temperature range

•

Packaging Information:

ASM3P623Z05: 8 pin SOIC, and TSSOP

ASM3P623Z09:16 pin SOIC, and TSSOP

•

True Drop-in Solution for Zero Delay Buffer,

ASM5P2305A / 09A

Functional Description

PCS3P623Z05/09 is a versatile, 3.3V Zero-delay buffer

designed to distribute Timing-Safe™ clocks with Peak EMI

reduction. PCS3P623Z05 is an eight-pin version, accepts

one reference input and drives out five low-skew Timing-

Safe™ clocks. PCS3P623Z09 accepts one reference input

and drives out nine low-skew Timing-Safe™clocks.

PCS3P623Z05/09 has a DLY_CTRL for adjusting the

Input-Output clock delay, depending upon the value of

capacitor connected at this pin to GND.

PCS3P623Z05/09 operates from a 3.3V supply and is

available in two different packages, as shown in the

ordering information table, over commercial and Industrial

temperature range.

Application

PCS3P623Z05/09 is targeted for use in Displays and

memory interface systems.

General Block Diagram

PLL

DLY_CTRL

CLKOUT1

CLKOUT2

CLKOUT3

CLKOUT4

PCS3P623Z05A/B

CLKIN

CLKIN

DLY_CTRL

PLL

MUX

CLKOUTA1

CLKOUTA2

CLKOUTA3

CLKOUTA4

CLKOUTB1

CLKOUTB2

CLKOUTB3

CLKOUTB4

Select Input

Decoding

S2

S1

PCS3P623Z09A/B