PCS5I9351G-32-ET datasheet(6/13 Pages) PULSECORE

Part #	PCS5I9351G-32-ET

Description	2.5V or 3.3V, 200MHz, 9-Output Zero Delay Buffer

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Manufacturer	PULSECORE [PulseCore Semiconductor]

Direct Link	http://www.onsemi.com/

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6 / 13 page

November 2006

PCS5I9351

rev 0.3

2.5V or 3.3V, 200MHz, 9-Output Zero Delay Buffer

6 of 13

Notice: The information in this document is subject to change without notice.

AC Electrical Specifications (V

DD = 2.5V ± 5%, TA = -40°C to +85°C)

1

Parameter

Description

Condition

Min

Typ

Max

Unit

fVCO

VCO Frequency

200

380

MHz

÷2 Feedback

100

190

÷4 Feedback

50

95

÷8 Feedback

25

47.5

fin

Input Frequency

Bypass mode (PLL_EN = 0)

0

200

MHz

frefDC

Input Duty Cycle

25

75

%

VPP

Peak-Peak Input Voltage

LVPECL

500

1000

mV

VCMR

Common Mode Range

2

LVPECL

1.2

VDD- 0.6

V

tr, tf

TCLK Input Rise/FallTime

0.7V to 1.7V

1.0

nS

÷2 Output

100

190

÷4 Output

50

95

fMAX

Maximum Output Frequency

÷8 Output

25

47.5

MHz

fMAX < 100MHz

47.5

52.5

DC

Output Duty Cycle

fMAX > 100MHz

45

55

%

tr, tf

Output Rise/Fall times

0.6V to 1.8V

0.1

1.0

nS

TCLK to FB_IN

-100

100

t(φ)

Propagation Delay

(static phase offset)

PCLK to FB_IN

-100

100

pS

tsk(O)

Output-to-Output Skew

150

pS

tPLZ, HZ

Output Disable Time

10

nS

tPZL, ZH

Output Enable Time

10

nS

÷2 Feedback

2.2

÷4 Feedback

0.85

BW

PLL Closed Loop Bandwidth

(–3dB)

÷8 Feedback

0.6

MHz

Same frequency

150

tJIT(CC)

Cycle-to-Cycle Jitter

Multiple frequencies

250

pS

Same frequency

100

tJIT(PER)

Period Jitter

Multiple frequencies

175

pS

tJIT(φ)

I/O Phase Jitter

175

pS

tLOCK

Maximum PLL Lock Time

1

mS

Note: 1 AC characteristics apply for parallel output termination of 50Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested.

2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input

swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(φ).

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