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PCS5I9658G-32-LR Datasheet(PDF) 5 Page - PulseCore Semiconductor |
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PCS5I9658G-32-LR Datasheet(HTML) 5 Page - PulseCore Semiconductor |
5 / 15 page November 2006 PCS5I9658 rev 0.3 3.3V 1:10 LVCMOS PLL Clock Generator 5 of 15 Notice: The information in this document is subject to change without notice. Table 5: DC Characteristics (V CC = 3.3V ± 5%, TA = -40°C to +85°C) Symbol Characteristics Min Typ Max Unit Condition VIH Input high voltage 2.0 VCC +0.3 V LVCMOS VIL Input low voltage 0.8 V LVCMOS VPP Peak-to-peak input voltage (PCLK) 250 mV LVPECL VCMR 1 Common Mode Range (PCLK) 1.0 VCC-0.6 V LVPECL VOH Output High Voltage 2.4 V IOH=-24 mA 2 VOL Output Low Voltage 3 0.55 0.30 V V IOL=24mA IOL=12mA ZOUT Output impedance 14 -17 Ω IIN Input Current 4 ±200 µA VIN=VCC or GND ICC_PLL Maximum PLL Supply Current 12 15 mA VCC_PLL Pin ICCQ Maximum Quiescent Supply Current 13 15 mA All VCC Pins Note: 1. VCMR (DC) is the cross point of the differential input signal. Functional operation is obtained ,when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2.The PCS5I9658 is capable of driving 50Ωtransmission lines on the incident edge. Each output drives one 50Ωparallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ωseries terminated transmission lines. 3.The PCS5I9658 output levels are compatible to the MPC958 output levels. 4.Inputs have pull-down or pull-up resistors affecting the input current. |
Similar Part No. - PCS5I9658G-32-LR |
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Similar Description - PCS5I9658G-32-LR |
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