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PCS5P9772G-52-ET Datasheet(PDF) 11 Page - PulseCore Semiconductor |
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PCS5P9772G-52-ET Datasheet(HTML) 11 Page - PulseCore Semiconductor |
11 / 15 page September 2006 PCS5I9772 rev 0.4 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer 11 of 15 Notice: The information in this document is subject to change without notice. Figure 2. D0-D3 are the control bits for QA0-QA3, respectively D4-D7 are the control bits for QB0-QB3, respectively D8-D10 are the control bits for QC1-QC3, respectively D11 is the control bit for SYNC Table 7. Suggested Oscillator Crystal Parameters Parameter Description Conditions Min Typ Max Unit TC Frequency Tolerance - - ±1100 PPM TS Frequency Temperature Stability (TA–10° to +60°C) - - ± 100 PPM TA Aging (First three years @ 25°C) - - 5 PPM/Yr CL Load Capacitance The crystal’s rated load - 20 - pF RESR Effective Series Resistance (ESR) - 40 80 Ohm Figure 3. LVCMOS_CLK AC Test Reference for VDD = 3.3V/2.5V Figure 4. LVCMOS Propagation Delay t( φ), Static Phase Offset D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 Start Bit LVCMOS_CLK VDD VDD VDD/2 VDD/2 GND GND t( φ) FB_IN Pulse Generator Z = 50 ohm Zo = 50 ohm RT = 50 ohm VTT VTT Zo = 50 ohm RT = 50 ohm |
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