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PCS5I9774 Datasheet(PDF) 9 Page - PulseCore Semiconductor |
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PCS5I9774 Datasheet(HTML) 9 Page - PulseCore Semiconductor |
9 / 12 page September 2006 PCS5I9774 rev 0.4 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer 9 of 12 Notice: The information in this document is subject to change without notice. Figure 1. LVCMOS_CLK AC Test Reference for VDD = 3.3V/2.5V Figure 2. LVCMOS Propagation Delay t(φ), Static Phase Offset DC = tP / T0 x 100% Figure 3. Output Duty Cycle (DC) Figure 4. Output-to-Output Skew, tsk(O) VDD VDD/2 GND tP T0 t SK(0) VDD VDD/2 GND VDD VDD/2 GND Pulse Generator Z = 50 ohm Zo = 50 ohm RT = 50 ohm VTT VTT Zo = 50 ohm RT = 50 ohm LVCMOS_CLK VDD VDD VDD/2 VDD/2 GND GND t( φ) FB_IN |
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