September 2006

PCS5I9773

rev 0. 4

2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer

4 of 16

Notice: The information in this document is subject to change without notice.

‘SpreadTrak’

Many systems being designed now utilize a technology

called Spread Spectrum Frequency Timing Generation.

PCS5I9773 is designed so as not to filter off the Spread

Spectrum feature of the Reference Input, assuming it

exists.

When a zero delay buffer is not designed to pass the

Spread Spectrum feature through, the result is a

significant amount of tracking skew which may cause

problems in the systems requiring synchronization.

Table 1: Frequency Table

Feedback

Output Divider

VCO

Input Frequency Range

(AVDD = 3.3V)

Input Frequency Range

(AVDD = 2.5V)

÷4

Input Clock * 4

50MHz to 125MHz

50MHz to 95MHz

÷6

Input Clock * 6

33.3MHz to 83.3MHz

33.3MHz to 63.3MHz

÷8.

Input Clock * 8

25MHz to 62.5MHz

25MHz to 47.5MHz

÷10

Input Clock * 10

20MHz to 50MHz

20MHz to 38MHz

÷12

Input Clock * 12

16.6MHz to 41.6MHz

16.6MHz to 31.6MHz

÷16

Input Clock * 16

12.5MHz to 31.25MHz

12.5MHz to 23.75MHz

÷20

Input Clock * 20

10MHz to 25MHz

10 MHz to19MHz

÷24

Input Clock * 24

8.3MHz to 20.8MHz

8.3MHz to 15.8MHz

÷32

Input Clock * 32

6.25MHz to 15.625MHz

6.25MHz to 11.8MHz

÷40

Input Clock * 40

5MHz to 12.5MHz

5MHz to 9.5MHz

Table 2. Function Table (Configuration Controls)

Control

Default

0

1

REF_SEL

1

TCLK0, TCLK1

PECL_CLK

TCLK_SEL

1

TCLK0

TCLK1

VCO_SEL

1

VCO÷2 (low input frequency range)

VCO÷1

(high input frequency range)

PLL_EN

1

Bypass mode, PLL disabled. The input clock connects to

the output dividers

PLL enabled. The VCO output

connects to the output dividers

INV_CLK

1

QC2 and QC3 are in phase with QC0 and QC1

QC2 and QC3 are inverted

(180° phase shift) with respect to

QC0 and QC1

MR#/OE

1

Outputs disabled (three-state) and reset of the device.

During reset/output disable the PLL feedback loop is open

and the VCO running at its minimum frequency. The device

is reset by the internal power-on reset (POR) circuitry

during power-up.

Outputs enabled