May 2007

PCS5P23Z05B/09B

rev 0.2

Notice: The information in this document is subject to change without notice.

PulseCore Semiconductor Corporation

1715 S. Bascom Ave Suite 200 Campbell, CA 95008

• Tel: 408-879-9077 • Fax: 408-879-9018

www.pulsecoresemi.com

Timing-Safe™ Peak EMI reduction IC

General Features

•

Clock distribution with Timing-Safe™ Peak EMI

Reduction

•

Input frequency range: 20MHz - 50MHz

•

Zero input - output propagation delay

•

Low-skew outputs

• Output-output skew less than 250pS

• Device-device skew less than 700pS

•

Less than 200pS cycle-to-cycle jitter

•

Available in 16pin, 150mil SOIC, 4.4mm TSSOP

(PCS5P23Z09B), and in 8pin, 150 mil SOIC,

4.4mm TSSOP Packages (PCS5P23Z05B)

•

3.3V Operation

•

Industrial temperature range

•

Advanced CMOS technology

•

The First True Drop-in Solution

Functional Description

PCS5P23Z05B/09B is a versatile, 3.3V zero-delay buffer

designed to distribute high-speed Timing-Safe™ clocks

with Peak EMI Reduction. PCS5P23Z09B accepts one

reference input and drives out nine low-skew clocks. It is

available in a 16pin Package. The PCS5P23Z05B is the

eight-pin version and accepts one reference input and

drives out five low-skew clocks.

All parts have on-chip PLLs that lock to an input clock on

the CLKIN pin. The PLL feedback is on-chip and is

obtained from the CLKOUT pad, internal to the device.

Multiple PCS5P23Z05B/09B devices can accept the same

input clock and distribute it. In this case, the skew between

the outputs of the two devices is guaranteed to be less than

700pS.

All outputs have less than 200pS of cycle-to-cycle jitter.

The input and output propagation delay is guaranteed to be

less than ±350pS, and the output-to-output skew is

guaranteed to be less than 250pS.

Refer

Table”

for deviations and Input-Output Skew for

PCS5P23Z05B and PCS5P23Z09B devices

The PCS5P23Z05B and PCS5P23Z09B are available in

two different packages, as shown in the ordering

information table.

Block Diagram

PCS5P23Z09B

PLL

MUX

CLKOUT

CLKA1

CLKA2

CLKA3

CLKA4

CLKB1

CLKB2

CLKB3

CLKB4

Select Input

Decoding

S2

S1

CLKIN

PLL

CLKOUT

CLK1

CLK2

CLK3

CLK4

PCS5P23Z05B

CLKIN