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TPIC46L03 Datasheet(PDF) 10 Page - Texas Instruments |
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TPIC46L03 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 19 page TPIC46L01, TPIC46L02, TPIC46L03 6-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER SLIS055A – NOVEMBER 1996 - REVISED SEPTEMBER 1997 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION serial data operation (continued) Data is shifted out of SDO on the falling edge of SCLK. The MSB of fault data is available when CS is transitioned low. The remaining 7 bits of fault data are shifted out on the following seven clock cycles. Fault data is latched into the serial register when CS is transitioned low. Fault data must be present on the high-to-low transition of CS to be captured by the device. The CS input must be transitioned to a high state after the last bit of serial data has been clocked into the device. CS puts SDO in a high-impedance state, inhibits SDI, latches the 6 bits of serial data into the output control register, and clears and re-enables the serial fault registers (see Figure 13). When a shorted-load condition occurs with the TPIC46L01 or TPIC46L03, the controller must disable and re-enable the channel to clear the fault register and fault flag. The TPIC46L02 automatically retries the output and FLT clears after the fault condition has been corrected. 12 3 4 5 6 7 8 OV Over-Battery-Voltage Fault Bit UV Under-Battery-Voltage Fault Bit FLT5 Shorted- or Open-Load Fault on Channel 5 FLT4 Shorted- or Open-Load Fault on Channel 4 FLT3 Shorted- or Open-Load Fault on Channel 3 FLT2 Shorted- or Open-Load Fault on Channel 2 FLT1 Shorted- or Open-Load Fault on Channel 1 FLT0 Shorted- or Open-Load Fault on Channel 0 N/A Unknown Data SCLK CS SDO 3-State UV FLT5 FLT4 FLT3 FLT2 FLT1 FLT0 N/A O V bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit8 Figure 13 parallel input data operation In addition to the serial input interface, the TPIC46L01 and TPIC46L02 also provides a parallel input interface to the microcontroller. The output turns on if either the parallel or the serial interface commands it to turn on. The parallel data pins are real-time control inputs for the output drivers. SCLK and CS are not required to transfer parallel input data to the output buffer. Fault data must be read over the serial data bus as described in the serial data operation section of this data sheet. The parallel input must be transitioned low and then high to clear and re-enable a gate output that has been disabled due to a shorted-load fault condition. |
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