TPS5211

HIGH FREQUENCY PROGRAMMABLE HYSTERETIC

REGULATOR CONTROLLER

SLVS243 – SEPTEMBER 1999

4

POST OFFICE BOX 655303

detailed description

The reference/voltage identification (VID) section consists of a temperature-compensated bandgap reference

and a 5-bit voltage selection network. The 5 VID terminals are inputs to the VID selection network and are

to the Intel

VRM 8.3 DC-DC Converter Specification for voltage settings between 1.8 V and 3.5 V, and they are

is within

±1.5% of the nominal setting over the VID range of 1.3 V to 2.5 V, including a junction temperature range

of 5

slowstart section for additional information.

hysteretic comparator

The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is

to ANAGND, with the output voltage connecting to the VHYST pin. The hysteresis of the comparator will be

equal to twice the voltage

difference between the VREFB and VHYST pins. The propagation delay from the

comparator inputs to the driver outputs is 250 ns (maximum). The maximum hysteresis setting is 60 mV.

low-side driver

The low-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is

2 A, source and sink. The bias to the low-side driver is internally connected to the DRV regulator.

high-side driver

The high-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is

2 A, source and sink. The high-side driver can be configured either as a ground-referenced driver or as a floating

bootstrap driver. When configured as a floating driver, the bias voltage to the driver is developed from the DRV

regulator. The internal bootstrap diode, connected between the DRV and BOOT pins, is a Schottky for improved

drive efficiency. The maximum voltage that can be applied between BOOT and DRVGND is 30 V. The driver

The rms current through the drivers output should not exceed 110 mA. Refer to the application information

section to determine how to calculate an operating frequency to meet this requirement.

deadtime control

Deadtime control prevents shoot-through current from flowing through the main power FETs during switching

transitions by actively controlling the turnon times of the MOSFET drivers. The high-side driver is not allowed

to turn on until the gate-drive voltage to the low-side FETs is below 2 V; the low-side driver is not allowed to turn

on until the voltage at the junction of the high-side and low-side FETs (Vphase) is below 2 V.