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TPS77133DGK Datasheet(PDF) 6 Page - Texas Instruments |
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TPS77133DGK Datasheet(HTML) 6 Page - Texas Instruments |
6 / 23 page TPS77101, TPS77118, TPS77127, TPS77128, TPS77133 WITH RESET OUTPUT TPS77201, TPS77218, TPS77227, TPS77228, TPS77233 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH INTEGRATED RESET OR PG SLVS225A – FEBRUARY 2000 – REVISED MARCH 2000 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS772xx PG timing diagram † Vres is the minimum input voltage for a valid PG. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology. VI Vres† Vres t t t VO Threshold Voltage PG Output Output Undefined Output Undefined VIT +‡ VIT –‡ VIT –‡ VIT +‡ ‡ VIT –Trip voltage is typically 18% lower than the output voltage (82%VO) VIT– to VIT+ is the hysteresis voltage. |
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