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SN65LVCP418PAPT Datasheet(PDF) 3 Page - Texas Instruments |
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SN65LVCP418PAPT Datasheet(HTML) 3 Page - Texas Instruments |
3 / 25 page SN65LVCP418 www.ti.com....................................................................................................................................................................................................... SLLS856 – JUNE 2009 PIN FUNCTIONS PIN TYPE DESCRIPTION NAME NO. HIGH SPEED I/O 5, 8, 11, 14, xA 18, 21, 24 Differential Inputs (with 50- Ω ,27 termination to Vbb) xA=P; Line Side Differential Inputs CML compatible 6, 9, 12, 15, xB=N xB 19, 22, 25, 28 34, 37, 40 xY 43, 51, 54, 57, 60 Differential Output xY=P; Switch Side Differential Outputs. VML xZ=N 33, 36, 39, xZ 42, 50, 53, 56, 59 CONTROL SIGNALS SCL 45 SDA 46 Inputs I2C Control Interface (SCL: Clock, SDA: Data, ADDR: Address) ADDR1 47 ADDR2 48 EQ 31 Input Equalization setting when I2C is not enabled. EQ=0 13dB and EQ=1 for 9dB Pre-Emphasis setting when I2C is not enabled. PRE=0 for 0 dB and PRE=1 PRE 32 Input for 6 dB Enables I2C control interface I2C_EN=1 for enable; When EN=0 then the I2C_EN 63 Input PRE and EQ pins are used to set the Pre-Emphasis and Equalization settings rather than the I2C register map. NC 62 Input No Connect Configuration Reset. Resets I2C register space; Note upon device startup RESN 3 Input (Active Low) the RESN pin must be driven low to reset the device registers. POWER SUPPLY 2, 7, 13, 20, 26, 30, 35, VCC Power Power Supply 3.3v±5% 41, 52, 58, 64 1,4, 10, 17, 23, 29 , 38, GND Ground 44, 49, 55, 61 PowerPAD™ Ground The ground center pad of the package must be connected to GND plane. VBB 16 Input Receiver input biasing voltage Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): SN65LVCP418 |
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