DESCRIPTION (CONTINUED)

ABSOLUTE MAXIMUM RATINGS

(1)

SN75LVDS83B

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

The SN75LVDS83B requires no external components and little or no control. The data bus appears the same at

the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The

only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a

low-level input, and the possible use of the Shutdown/Clear (SHTDN). SHTDN is an active-low input to inhibit the

clock, and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all

internal registers to a low-level.

The SN75LVDS83B is characterized for operation over ambient air temperatures of -10°C to 70°C.

Alternative device option: The SN75LVDS83A (SLLS980) is an alternative to the SN75LVDS83B for clock

frequency range of 10MHz-100MHz only. The SN75LVDS83A is available in the TSSOP package option only.

PART NUMBER

PART MARKING

PACKAGE

SN75LVDS83BZQLR

LVDS83B in BGA package

56-pin ZQL LARGE T&R

SN75LVDS83BDGG

LVDS83B in TSSOP package

56-pin DGG TUBE

SN75LVDS83BDGGR

LVDS83B in TSSOP package

56-pin DGG LARGE T&R

(1)

For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or

refer to our web site at www.ti.com.

VALUE

UNIT

-0.5 to 4

V

Voltage range at any output terminal

-0.5 to VCC + 0.5

V

Voltage range at any input terminal

-0.5 to IOVCC + 0.5

V

Continuous power dissipation

See the dissipation rating table

5

kV

ESD rating

500

V

150

V

(1)

Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those specified is not implied.

(2)

All voltages are with respect to the GND terminals.

(3)

In accordance with JEDEC Standard 22, Test Method A114-A.

(4)

In accordance with JEDEC Standard 22, Test Method C101.

(5)

In accordance with JEDEC Standard 22, Test Method A115-A.

2

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