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TAS5630DKDR Datasheet(PDF) 10 Page - Texas Instruments |
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TAS5630DKDR Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 31 page  AUDIO SPECIFICATION (PBTL) ELECTRICAL CHARACTERISTICS TAS5630 SLES220 – JUNE 2009 ...................................................................................................................................................................................................... www.ti.com PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL = 2Ω, fS = 400 kHz, ROC = 22 kΩ, TC = 75°C, Output Filter: LDEM = 7 µH, CDEM = 1.5 µF, MODE = 101-10, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RL = 2 Ω, 10% THD+N, clipped output signal 600 RL = 3 Ω, 10% THD+N, clipped output signal 400 RL = 4 Ω, 10% THD+N, clipped output signal 300 PO Power output per channel W RL = 2 Ω, 1% THD+N, unclipped output signal 480 RL = 3 Ω, 1% THD+N, unclipped output signal 310 RL = 4 Ω, 1% THD+N, unclipped output signal 230 THD+N Total harmonic distortion + noise 1 W 0.05% Vn Output integrated noise A-weighted 260 µV SNR Signal to noise ratio(1) A-weighted 100 dB DNR Dynamic range A-weighted 100 dB Pidle Power dissipation due to idle losses (IPVDD_X) PO = 0, 4 channels switching (2) 2.7 W (1) SNR is calculated relative to 1% THD-N output level. (2) Actual system idle losses are affected by core losses of output inductors. PVDD_X = 50 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 400 kHz, unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION Voltage regulator, only used as reference VREG VDD = 12 V 3 3.3 3.6 V node, VREG VI_CM Analog comparator reference node, VI_CM 1.5 1.75 1.9 V Operating, 50% duty cycle 22.5 IVDD VDD supply current mA Idle, reset mode 22.5 50% duty cycle 12.5 IGVDD_X GVDD_x gate-supply current per half-bridge mA Reset mode 1.5 50% duty cycle with recommended output 13.3 mA filter IPVDD_X Half-bridge supply current Reset mode, No switching 870 µA ANALOG INPUTS RIN Input resistance READY = HIGH 33 k Ω VIN Maximum input voltage swing 5 V IIN Maximum input current 342 µA G Voltage Gain (VOUT/VIN) 23 dB OSCILLATOR Nominal, Master Mode 3.5 4 4.5 fOSC_IO+ AM1, Master Mode FPWM × 10 3.1 3.4 3.5 MHz AM2, Master Mode 2.6 3 3.2 VIH High level input voltage 1.86 V VIL Low level input voltage 1.45 V OUTPUT-STAGE MOSFETs Drain-to-source resistance, low side (LS) 60 100 m Ω TJ = 25°C, excludes metallization RDS(on) resistance, GVDD = 12 V Drain-to-source resistance, high side (HS) 60 100 m Ω 10 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5630 |
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