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74AVCH4T245PW Datasheet(PDF) 4 Page - NXP Semiconductors |
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74AVCH4T245PW Datasheet(HTML) 4 Page - NXP Semiconductors |
4 / 26 page 74AVCH4T245_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 6 August 2009 4 of 26 NXP Semiconductors 74AVCH4T245 4-bit dual supply translating transceiver; 3-state 5.2 Pin description [1] All GND pins must be connected to ground (0 V). (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration SOT403-1 (TSSOP16) Fig 5. Pin configuration SOT763-1 (DHVQFN16) 74AVCH4T245 VCC(A) VCC(B) 1DIR 1OE 2DIR 2OE 1A1 1B1 1A2 1B2 2A1 2B1 2A2 2B2 GND GND 001aak287 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 001aak289 74AVCH4T245 2A2 2B2 2A1 2B1 1A2 1B2 1A1 1B1 2DIR 2OE 1DIR 1OE Transparent top view 7 10 6 11 5 12 4 13 3 14 2 15 terminal 1 index area GND(1) Table 2. Pin description Symbol Pin Description VCC(A) 1 supply voltage A (nAn, nOE and nDIR inputs are referenced to VCC(A)) 1DIR, 2DIR 2, 3 direction control 1A1, 1A2 4, 5 data input or output 2A1, 2A2 6, 7 data input or output GND[1] 8, 9 ground (0 V) 2B2, 2B1 10, 11 data input or output 1B2, 1B1 12, 13 data input or output 2OE, 1OE 14, 15 output enable input (active LOW) VCC(B) 16 supply voltage B (nBn inputs are referenced to VCC(B)) |
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