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UCC18500 Datasheet(PDF) 6 Page - Texas Instruments |
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UCC18500 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 8 page 6 UCC18500/1/2/3 UCC28500/1/2/3 UCC38500/1/2/3 The UCC38500 is designed to incorporate all the control functions required for a power factor correction circuit and a second stage dc-dc converter. The PFC function is implemented as a full feature, average current mode controller Integrated Circuit for excellent performance. In addition, the input voltage feedforward function is imple- mented in a simplified manner. Current from IAC is mir- rored over to the VFF pin. By simply adding a resistor and capacitor (to attenuate 120Hz ripple) a voltage is de- veloped which is proportional to line voltage. This elimi- nates several components normally connected to the line. The UCC38500 uses leading edge modulation for the PFC stage and trailing edge modulation for the dc-dc stage. This reduces ripple current in the output capacitor by reducing the overlap in conduction time of the PFC and dc-dc switches. In addition to the reduced ripple cur- rent, noise immunity is improved through the current er- ror amplifier implementation. The UCC38500 is optimized to control a boost PFC stage operating in continuous conduction mode, followed by a dc-dc converter (typically a forward topology). It is usual that the dc-dc converter is transformer isolated and therefore its error amplifier will be located on the second- ary side. The UCC38500 is configured without an inter- nal error amplifier. The externally generated error signal is fed into the VERR pin. The UCC38500 can be configured for voltage mode or current mode control of the second stage. The applica- tion figure shows a typical current mode configuration. For voltage mode control the ramp generated by CT is simply fed into the ISENSE2 pin. One of the main system challenges in designing systems with a PFC front end is coordinating the turn-on and turn-off on the dc-dc converter. If the dc-dc converter is allowed to turn on before the boost converter is opera- tional, it must operate at a much-reduced voltage and therefore can represent a large current draw to the boost converter. This start-up sequencing is handled internally by the UCC38500. The UCC38500 monitors the output voltage of the PFC converter and holds the dc-dc con- verter off until the output is within 10% of its regulation point. Once the trip point is reached the dc-dc section goes through a soft start sequence for a controlled, low stress start-up. Similarly if the output voltage drops too low (2 voltage options are available) the dc-dc converter shuts down thereby preventing overstress of the con- verter. Design details of the PFC section can be found in several references shown below. • UCC3817 data sheet • High Power Factor Preregulator for Off-Line Power Supplies, SEM-800 • Optimizing the Design of a High Power Factor Switching Regulator, SEM-800 A design example fora2switch forward converter can be found in: • 250W Off-Line Forward Converter Design Review, SEM-500 APPLICATION INFORMATION R VFF IAC VFF MAX MAX = •• 2 2 09 . VSENSE: (voltage amplifier inverting input) This is nor- mally connected to a compensation network and to the boost converter output through a divider network. VREF: (voltage reference output) VREF is the output of an accurate 7.5V voltage reference. This output is capa- ble of delivering 10mA to peripheral circuitry and is inter- nally short circuit current limited. VREF is disabled and will remain at 0V when VCC is below the UVLO thresh- old. Bypass VREF to GND with a 0.1 µF or larger ceramic capacitor for best stability. PIN DESCRIPTIONS |
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