UCC18500/1/2/3

UCC28500/1/2/3

UCC38500/1/2/3

PRELIMINARY

DESCRIPTION

The UCC18500 family provides all of the functions necessary for an ac-

tive power factor corrected preregulator and a second stage DC-to-DC

converter. The controller achieves near-unity power factor by shaping

the AC input line current waveform to correspond to the AC input line

voltage using average current mode control. The DC-to-DC converter

uses peak current mode control to perform the step down power con-

version.

The PFC stage is leading edge modulated while the second stage is

trailing edge synchronized to allow for minimum overlap between the

boost and PWM switches. This reduces ripple current in the bulk output

capacitor.

In order to operate with a three to one range of input line voltages, a

with an external single pole filter. This not only reduces external parts

count, but avoids the use of high voltage components offering a lower

cost solution. The multiplier then divides the line current by the square

(continued)

BiCMOS PFC/PWM Combination Controller

FEATURES

Converter Function

• Controls Boost PWM to Near-unity Power

Factor

• Accurate Power Limiting

• Average Current Mode Control in PFC

Stage

• Peak Current Mode Control in Second

Stage

• Programmable Oscillator

• Leading Edge/Trailing Edge Modulation

for Reduced Output Ripple Using

SmartSync™

• Low Startup Supply Current

• Synchronized Second Stage Start-up,

with Programmable Soft-start

• Programmable Second Stage Shut-down

SLUS419 - AUGUST 1999

VREF

20

14

12

11

9

4

17

16

GT1

PWRGND

ISENSE1

VCC

OVP/ENBL

VAOUT

1.5V

PKLMT

7.5V

REFERENCE

UVLO

16V/10

+

–

VCC

15

OSCILLATOR

2

RT

5

CT

S

Q

R

PWM

LATCH

+

–

PWM

CAOUT

+

–

+

–

+

–

SS2

VOLTAGE

ERROR AMP

8.0V

13

1

3

VSENSE

VFF

19

IAC

18

MOUT

MIRROR

2:1

+

–

7.5V

ENABLE

PFCOVP

÷

X

X

MULT

CLK1

CURRENT AMP

6.75V

6

GND

10

GT2

VCC

7

8

SECOND STAGE

SOFT START

CLK2

1.5V 1.3V

R

I

LIMIT

CLK2

OSC

CLK1

CLK2

VERR ISENSE2

I

LIMIT

S

Q

R

R

UVLO2

PWM

+

–

0.25V

(V

2

ZERO

POWER

BLOCK DIAGRAM

UDG-98189