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CY62126EV30 Datasheet(PDF) 5 Page - Cypress Semiconductor

Part # CY62126EV30
Description  1-Mbit (64K x 16) Static RAM
Download  13 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY62126EV30 Datasheet(HTML) 5 Page - Cypress Semiconductor

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MoBL®, CY62126EV30
Document #: 38-05486 Rev. *E
Page 5 of 13
Switching Characteristics
Over the Operating Range [10, 11]
Parameter
Description
45 ns (Industrial)
55 ns (Automotive)
Unit
Min
Max
Min
Max
Read Cycle
tRC
Read Cycle Time
45
55
ns
tAA
Address to Data Valid
45
55
ns
tOHA
Data Hold from Address Change
10
10
ns
tACE
CE LOW to Data Valid
45
55
ns
tDOE
OE LOW to Data Valid
22
25
ns
tLZOE
OE LOW to Low Z [12]
55
ns
tHZOE
OE HIGH to High Z [12, 13]
18
20
ns
tLZCE
CE LOW to Low Z [12]
10
10
ns
tHZCE
CE HIGH to High Z [12, 13]
18
20
ns
tPU
CE LOW to Power Up
0
0
ns
tPD
CE HIGH to Power Down
45
55
ns
tDBE
BHE / BLE LOW to Data Valid
22
25
ns
tLZBE
BHE / BLE LOW to Low Z [12]
55
ns
tHZBE
BHE / BLE HIGH to High Z [12, 13]
18
20
ns
Write Cycle [14]
tWC
Write Cycle Time
45
55
ns
tSCE
CE LOW to Write End
35
40
ns
tAW
Address Setup to Write End
35
40
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Setup to Write Start
0
0
ns
tPWE
WE Pulse Width
35
40
ns
tBW
BHE / BLE Pulse Width
35
40
ns
tSD
Data Setup to Write End
25
25
ns
tHD
Data Hold from Write End
0
0
ns
tHZWE
WE LOW to High Z [12, 13]
18
20
ns
tLZWE
WE HIGH to Low Z [12]
10
10
ns
Notes
10. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the
specified IOL/IOH and 30-pF load capacitance.
11. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
12. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
13. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
14. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of
these signals can terminate a write by going inactive. The data input setup and hold timing must refer to the edge of signal that terminates write.
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