5

UCC1895

UCC2895

UCC3895

PIN DESCRIPTIONS

ADS: Adaptive Delay Set. This function sets the ratio be-

tween the maximum and minimum programmed output

delay dead time. When the ADS pin is directly connected

to the CS pin, no delay modulation occurs. The maximum

delay modulation occurs when ADS is grounded. In this

case, delay time is four times longer when CS = 0 than

when CS = 2.0V (the Peak Current threshold), ADS

changes the output voltage on the delay pins DELAB and

DELCD by the following formula:

()

[]

VV

V

V

DEL

CS

ADS

=•

−

+

075

0 5

..

between 0V and 2.5V and must be less than or equal to

CS. DELAB and DELCD also will be clamped to a mini-

mum of 0.5V.

EAOUT: Error Amplifier Output. It is also connected inter-

nally to the non-inverting input of the PWM comparator

and

the

no-load

comparator. EAOUT

is

internally

clamped to the soft start voltage. The no-load comparator

shuts down the output stages when EAOUT falls below

500mV, and allows the outputs to turn-on again when

EAOUT rises above 600mV.

CT: Oscillator Timing Capacitor. (Refer to Fig. 1, Oscilla-

tor Block Diagram) The UCC3895’s oscillator charges CT

sawtooth, with a peak voltage of 2.35V. The approximate

oscillator period is calculated by the following formula:

t

RC

ns

OSC

TT

=

••

+

5

48

120

creased fall time will increase the SYNC pulse width,

hence limiting the maximum phase shift between OUTA,

OUTB and OUTC, OUTD outputs, which limits the maxi-

mum duty cycle of the converter.

CS: Current Sense. This is the inverting input of the Cur-

rent Sense comparator and the non-inverting input of the

Over-current comparator, and the ADS amplifier. The cur-

rent sense signal is used for cycle-by-cycle current limit-

ing in peak current mode control, and for overcurrent

protection in all cases with a secondary threshold for out-

put

shutdown. An

output

disable

initiated

by

an

overcurrent fault also results in a restart cycle, called

“soft stop”, with full soft start.

DELAB,

DELCD:

Delay

Programming

Between

Complementary Outputs. DELAB programs the dead

time between switching of OUTA and OUTB, and DELCD

programs the dead time between OUTC and OUTD. This

delay is introduced between complementary outputs in

the same leg of the external bridge. The UCC3895 allows

the user to select the delay, in which the resonant

switching of the external power stages takes place.

Separate delays are provided for the two half-bridges to

accommodate differences in resonant capacitor charging

currents. The delay in each stage is set according to the

following formula:

()

t

R

V

ns

DELAY

DEL

DEL

=

••

+

−

25 10

25

12

is in seconds.

DELAB and DELCD can source about

1mA maximum. Choose the delay resistors so that this

maximum is not exceeded. Programmable output delay

For an optimum performance keep stray capacitance on

these pins at <10pF.

EAP: The non-inverting input to the error amplifier.

EAN: The inverting input to the error amplifier.

GND: Chip ground for all circuits except the output

stages.

OUTA, OUTB, OUTC, OUTD: The 4 outputs are 100mA

complementary MOS drivers, and are optimized to drive

FET

driver

circuits.

OUTA

and

OUTB

are

fully

complementary, (assuming no programmed delay). They

operate near 50% duty cycle and one-half the oscillating

frequency. OUTA and OUTB are intended to drive one

half-bridge circuit in an external power stage. OUTC and

OUTD will drive the other half-bridge and will have the

same characteristics as OUTA and OUTB. OUTC is

phase shifted with respect to OUTA, and OUTD is phase

shifted with respect to OUTB. Note that changing the

phase relationship of OUTC and OUTD with respect to

OUTA and OUTB requires other than the nominal 50%

duty ratio on OUTC and OUTD during those transients.

PGND: Output Stage Ground. To keep output switching

noise from critical analog circuits, the UCC3895 has 2

different ground connections. PGND is the ground

connection for the high-current output stages. Both GND

and PGND must be electrically tied together closely near

the IC. Also, since PGND carries high current, board

traces must be low impedance.