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UCC3830- Datasheet(PDF) 4 Page - Texas Instruments |
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UCC3830- Datasheet(HTML) 4 Page - Texas Instruments |
4 / 10 page 4 UCC3830-4/-5/-6 CAM (Current Amplifier Inverting Input): The average load current feedback from ISOUT is applied through a resistor to this pin. The current loop compensation network is also connected to this pin (see CAO/ENBL below). CAO/ENBL (Current Amplifier Output/Chip Enable): The current loop compensation network is connected between this pin and CAM. The voltage on this pin is the input to the PWM comparator and regulates the output voltage of the system. The GATE output is disabled (held low) unless the voltage on this pin exceeds 1V, allowing the PWM to force zero duty cycle when necessary. The PWM forces maximum duty cycle when the voltage on CAO/ENBL exceeds the oscillator peak voltage (3V). A 3.2V clamp circuit prevents the CAO/ENBL voltage from rising excessively past the oscillator peak voltage for excellent transient response. The user can force this pin below 0.8V externally with an open collector, disabling the GATE drive. COMMAND (Digital-to-Analog Converter Output Voltage): This pin is the output of the 5-bit digital-to-analog converter (DAC) and the noninverting input of the voltage amplifier. The voltage on this pin sets the switching regulator output voltage. This voltage ranges from 1.8V to 3.5V as programmed by the 5-bit DAC according to Table 1. The GATE output is disabled when all 1s or illegal codes are presented at the 5 Bit DAC. The COMMAND source impedance is typically 1.2k Ω and must therefore drive only high impedance inputs if accuracy is to be maintained. Bypass COMMAND with a 0.01 µF, low ESR, low ESL capacitor for best circuit noise immunity. COMP (Voltage Amplifier Output): The system voltage compensation network is applied between COMP and VFB. D0 - D4 (DAC Digital Input Control Codes): These are the DAC digital input control codes, with D0 representing the least significant bit (LSB) and D4, the most significant bit (MSB) as shown in Table 1. A bit is set low by being connected to GND. A bit is set high by floating it, or connecting it to a 5V source. Each control pin is pulled up to approximately 5V by an internal 70 µA current source. GATE (PWM Output, MOSFET Driver): This output provides a 4 Ω totem pole driver. Use a series resistor between this pin and the gate of the external MOSFET to prevent excessive overshoot. GND (Signal Ground): All voltages are measured with respect to GND. Bypass capacitors on the VCC and VREF pins should be connected directly to the ground plane near the GND pin. IS– (Current Sense Amplifier Inverting Input): This pin is the inverting input to the current sense amplifier and is connected to the low side of the average current sense resistor. IS+ (Current Sense Amplifier Noninverting Input): This pin is the noninverting input to the current sense amplifier and is connected to the high side of the average current sense resistor. ISOUT (Current Sense Amplifier Output): This pin is the output of the current sense amplifier. The voltage on this pin is (COMMAND + GCSA •I•RSENSE), where COMMAND is the voltage on the COMMAND pin, GCSA is the fixed gain of the current sense amplifier, equal to 15, I is the current through the sense resistor, and RSENSE is the value of the average current sensing resistor. PGND (Power Ground): This pin provides a dedicated ground for the output gate driver. The GND and PGND pins should be connected externally using a short printed circuit board trace close to the IC. Decouple VIN to PGND with a low ESR capacitor 0.10µF. PWRGOOD (Undervoltage/Lower Overvoltage Output): This pin is an open drain output which is driven low to reset the microprocessor when VSENSE rises above or falls below its nominal value by 8.5%. The on resistance of the open drain switch will be no higher than 470 Ω. The OV and UV comparators’ hysteresis is fixed at 20mV independent of the COMMAND voltage. VIN (Positive Supply Voltage): This pin supplies power to the chip. Connect VIN to a stable voltage source of at least 10.8V. The GATE and PWRGOOD outputs will be held low until VCC exceeds the upper undervoltage lockout threshold. This pin should be bypassed directly to the GND pin. VFB (Voltage Amplifier Inverting Input): This input is connected to COMP through a feedback network and to the power supply output through a resistor or a divider network. VREF (Voltage Reference Output): This pin provides an accurate 5V reference and is internally short circuit current limited. VREF powers the D/A converter and also provides a threshold voltage for the UVLO comparator. For best reference stability, bypass VREF directly to GND with a low ESR, low ESL capacitor of at least 0.01 µF. PIN DESCRIPTIONS |
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