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UCC3957-2 Datasheet(PDF) 2 Page - Texas Instruments |
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UCC3957-2 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 8 page 2 UCC3957 -1/-2/-3/-4 ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VDD = 16V and –20°C < TA < 70°C, TA = TJ. All voltages measured with respect to the AN4 terminal. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Supply Section Minimum VDD 5.0 5.5 V Supply Current 30 40 µA Sleep Mode Supply Current VDD = 10.4V 3.5 7.5 µA Output Section DCHG Output Current Driving Logic Low and VO = 1V 40 70 100 µA Driving Logic High and VO = VDD – 1 –20 –7 –3 mA CHG Ouput Current Driving Logic Low and VO = 1V 40 70 100 µA Driving Logic High and VO = VDD – 1V –20 –7 –3 mA State Transitions Normal to Overcharge UCC3957-1 4.15 4.20 4.25 V Overcharge to Normal UCC3957-1 3.95 4.00 4.05 V Normal to Overcharge UCC3957-2 4.20 4.25 4.30 V Overcharge to Normal UCC3957-2 4.00 4.05 4.10 V Normal to Overcharge UCC3957-3 4.25 4.30 4.35 V Overcharge to Normal UCC3957-3 4.05 4.10 4.15 V Normal to Overcharge UCC3957-4 4.30 4.35 4.40 V Overcharge to Normal UCC3957-4 4.10 4.15 4.20 V Undercharge to Normal 2.5 2.6 2.7 V Normal to Undercharge 2.2 2.3 2.4 V OV to CHG Delay (Note 1) 10 17 23 ms ABSOLUTE MAXIMUM RATINGS Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA Output Current (CHG, DCHG) . . . . . . . . . . . . . . . . . . . . . 25mA WU Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28V BATLO Input Voltage . . . . . . . . . . . . . . . . . . . . . . –0.3V to 2.5V AN1 and AN3 Input Voltage . . . . . . . . . . . . . . . . . VAN4 – VDD CLCNT and CHGEN . . . . . . . . . . . . . . . . . . . . . . . VAN4 – VDD Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . –55°C to +150°C Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C Unless otherwise indicated, voltages are referenced to AN4. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages. DESCRIPTION (continued) If at the end of the blanking time the overcurrent condi- tion still exists, the external discharge FET is turned off for a period 17 times longer than the first blanking pe- riod, and then the discharge FET is turned back on. If at any time a second higher overcurrent threshold is ex- ceeded for more than a user programmable time, the dis- charge FET is turned off, and will remain off for the same period as the first tier off time. This two tiered overcurrent protection scheme allows for charging capacitive loads while retaining effective short circuit protection. CDLY2 AVDD DVDD DCHG CHG CDLY1 AN4 CHGEN 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 CLCNT VDD BATLO AN3 AN4 WU AN1 AN2 CONNECTION DIAGRAM SSOP-16 (Top View) M Package |
Similar Part No. - UCC3957-2 |
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Similar Description - UCC3957-2 |
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