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UCC3911DP-1 Datasheet(PDF) 5 Page - Texas Instruments |
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UCC3911DP-1 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 12 page UCC3911-1, UCC3911-2 UCC3911-3, UCC3911-4 SLUS429B– FEBRUARY 2000 – REVISED NOVEMBER 2002 5 www.ti.com detailed pin descriptions CDLY: Delay control pin for the short circuit protection feature. A capacitor connected between this pin and the B0 pin lengthens the time delay from when an overcurrent situation is detected to when the protection circuitry is activated. This control will be useful for those applications where high-peak load currents may momentarily exceed the protection circuit’s threshold current and interruption of the battery current is undesirable. The nominal delay time is internally set at 100 µs. The equation for determining this delay is: t DLY ( ms) + 25 ) (25 ) CDLY (pF) ) 0.4 V B2 To recover from an overcurrent shutdown the load must be removed momentarily from the pack. CE: While the chip enable signal is held low, the internal FET is held off. CE is pulled high by a 2- µA current source. This function was included to facilitate construction of the battery pack. The last step in the electrical assembly of the pack is to cut a link grounding B0. With the CE pin connected to B0, the supply current drain is only about 4 µA. GND: The second of the two terminals that are presented to the user of the battery pack. The internal FET switch connects this terminal to the B0 terminal to give the battery pack user appropriate access to the cells. In an overvoltage state, current is allowed to flow only into this terminal. Similarly, in an undervoltage state, current is allowed to flow only out of this terminal. OV: This active-low signal indicates the state of the state machine’s overvoltage bit. When low, it indicates that one or both cells are overvoltage. Further charging is inhibited by the opening of the FET switch. The output buffer for this pin is sized to drive a very light load. UV: This active-low signal indicates the state of the state machine’s undervoltage bit. When low, it indicates that one or both cells are undervoltage. Further discharging is inhibited by the opening of the FET switch. The chip enters the sleep mode when UV goes low and waits in this state until the device detects that the battery pack has been placed in a charging circuit. The output buffer for this pin is sized to drive a very light load. (1) |
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Similar Description - UCC3911DP-1 |
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