UCC5950

UNITRODE INTEGRATED CIRCUITS

7 CONTINENTAL BLVD.

• MERRIMACK, NH 03054

TEL. (603) 424-2410

• FAX (603) 424-3460

SLOD

Internal Flag

SCLK

SDIO

Internal Count

Action

DACOUT

11

don’t care

don’t care

0

no action

V(t)

0

0

rising edge

DATA

<10

V(t)

0

0

rising edge

DATA

10

Set Internal Flag

Reset Count

V(t+1)

01

don’t care

don’t care

0

no action

V(t)

SERIAL DATA INTERFACE TIMING AND LOGIC TABLE

PIN DESCRIPTIONS

DACOUT: The output of the 10-bit D/A Converter. For

best settling time, minimize load capacitance.

DACOUT will go to a voltage between 1.094V and

3.208V depending on the digital code loaded into the

latches. The digital code follows this pattern:

Input Code

Typical DACOUT

Significance

1000000000

1.094V

Zero Scale

1000000001

1.096V

1000000010

1.098V

...

1111111111

2.151V

0000000000

2.153V

Mid Scale

0000000001

2.155V

...

0111111110

3.206V

0111111111

3.208V

Full Scale

GND: All signals are referenced to GND.

REFOUT: The output of the temperature-compensated

2.15V reference.

DO NOT BYPASS REFOUT! For best

stability and transient response, minimize capacitance on

REFOUT.

SCLK: Data is clocked into the D/A after SLOD goes low

on rising edges of SCLK. After 10 rising edges of SCLK,

the data is latched into the D/A output register and the

output is updated. Further clock signals on SCLK are ig-

nored until SLOD initiates a new read cycle.

SDIO: After SLOD goes low, data is clocked into the D/A

from the SDIO input, on rising edges of SCLK, LSB first.

After 10 rising edges, data is latched and converted, and

further SCLK and SDIO information is ignored.

SLEEP: SLEEP is the power-down input to the D/A. In

systems not requiring this function, wire SLEEP to GND.

SLOD: SLOD is the chip-select input to the UCC5950.

SLOD going low selects the D/A and enables clocking of

data from SDIO into the D/A. After 10 SCLK pulses, the

D/A is updated and SLOD is ignored until SLOD goes

high and again goes low.

VDD: All analog and digital functions are powered from

VDD. VDD should be a well-regulated supply to minimize

output variations. Bypass VDD to GND with a ceramic

capacitor very close to the UCC5950.

UDG-95035

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