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SPT5240SIT Datasheet(PDF) 2 Page - Cadeka Microcircuits LLC. |
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SPT5240SIT Datasheet(HTML) 2 Page - Cadeka Microcircuits LLC. |
2 / 10 page 2 REV. 1 June 2003 DATA SHEET SPT5240 TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. LEVEL TEST PROCEDURE I 100% production tested at the specified temperature. IV Parameter is guaranteed by design or characterization data. V Parameter is a typical value for information purposes only. Electrical Specifications (TA = 25°C, AVDD = 3.3V, DVDD = 3.3V, ƒOUT = 1.27MHz, ƒCLK = 400MHz, Clock Duty Cycle = 50%, IOUT = 20mA, RL = 50Ω; unless otherwise noted) Parameter Conditions Test Level Min Typ Max Units DC Performance Resolution 10 Bits Differential Linearity Error (DLE) DC at ION I-1 2 LSB Integral Linearity Error (ILE) DC at ION I-4 ±1.34 4 LSB Offset Error DC at both outputs I -.005 +.005 %FS Full Scale Error DC at both outputs I -15 +15 %FS Gain Error DC at both outputs I -15 +15 %FS Maximum Full Scale Output Current V 30 mA Output Compliance Voltage V 1.5 V Output Impedance Full-scale output V 250 kΩ Gain Error Tempco V ±300 ppm FS/°C AC Performance Maximum Clock Rate IV 400 MHz Glitch Energy Major code transition V 7 pV-s Settling Time (tsettling) See Figure 1, major code trans. V 7.5 ns Output Rise Time V 1.3 ns Output Fall Time V 1.5 ns Output Delay Time (tD) See Figure 1 V 1.8 ns Spurious Free Dynamic Range (SFDR) V58 dBc Total Harmonic Distortion (THD) V -55 dBc Digital and Clock Data Input VIH Minimum V 2 V VIL Maximum V 1 V Logic “1” Current I -10 +10 µA Logic “0” Current I -10 +10 µA Input Setup Time (tS) See Figure 1 V 1 ns Input Hold Time (tH) See Figure 1 V 1 ns Clock Feedthrough V -29 dBFS |
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