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SPT7721 Datasheet(PDF) 3 Page - Cadeka Microcircuits LLC.

Part # SPT7721
Description  8-BIT, 250 MSPS ADC WITH DEMUXED OUTPUTS
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Manufacturer  CADEKA [Cadeka Microcircuits LLC.]
Direct Link  http://www.cadeka.com
Logo CADEKA - Cadeka Microcircuits LLC.

SPT7721 Datasheet(HTML) 3 Page - Cadeka Microcircuits LLC.

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11/8/01
SPT7721
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
ELECTRICAL SPECIFICATIONS
TA = TMIN to TMAX, AVCC = +5.0 V, ƒCLK = 250 MHz, VCM = 2.5 V, OVDD = 5 V, unless otherwise specified.
TEST
TEST
SPT7721
PARAMETERS
CONDITIONS
LEVEL
MIN
TYP
MAX
UNITS
Dynamic Performance
Total Harmonic Distortion (THD)
ƒIN = 70 MHz
+25 °C
VI
–43
–40
dB
ƒIN = 70 MHz
–40 °C to +85 °C
IV
–42
–37
dB
Signal-to-Noise and Distortion (SINAD)
ƒIN = 70 MHz
+25 °C
VI
37
40
dB
ƒIN = 70 MHz
–40 °C to +85 °C
IV
35
38
dB
Power Supply Requirements
AVCC Voltage (Analog Supply)
IV
4.75
5.0
5.25
V
OVDD Voltage (Digital Supply)
IV
2.75
5.25
V
AVCC Current
VI
62
70
mA
Power Dissipation with Internal Voltage Reference
VI
310
350
mW
Common Mode Reference
Voltage
VI
2.45
2.5
2.55
V
Voltage Tempco
V
100
ppm/°C
Output Impedance
IOUT = ±50 µA
V
1
k
Power Supply Rejection Ratio
V
63
mV/V
Clock and Reset Inputs (Differential and Single-Ended)
Differential Signal Amplitude (VDIFF)
VI
400
mVP-P
Differential High Input Voltage (VIHD)
IV
1.4
5
V
Differential Low Input Voltage (VILD)
IV
0
3.9
V
Differential Common-Mode Input (VCMD)
IV
1.2
4.1
V
Single-Ended High Input Voltage (VIH)
IV
1.8
V
Single-Ended Low Input Voltage (VIL)
IV
1.2
V
Input Current High (IIH)
VID = 1.5 V
VI
–100
20
+100
µA
Input Current Low (IIL)
VID = 1.5 V
VI
–100
20
+100
µA
Power Down and Mode Control Inputs (Single-Ended)
High Input Voltage
IV
2.0
AVCC
V
Low Input Voltage
IV
0
1.0
V
Maximum Input Current Low
VI
–100
10
+100
µA
Maximum Input Current High <4.0 V
VI
–100
10
+100
µA
Digital Outputs
Logic "1" Voltage
IOH = –0.5 mA
VI
OVDD – 0.2 OVDD – 0.06
V
Logic "0" Voltage
IOL = +1.6 mA
VI
0.13
0.2
V
TR/TF Data
10 pF load
OVDD = 3 V
V
3.5
ns
OVDD = 5 V
V
2.0
ns
TR/TF DCLK = (10 pF load)
OVDD = 3 V
V
1.3
ns
OVDD = 5 V
V
0.7
ns
LEVEL
TEST PROCEDURE
I
100% production tested at the specified temperature.
II
100% production tested at TA = +25 °C, and sample tested at the
specified temperatures.
III
QA sample tested only at the specified temperatures.
IV
Parameter is guaranteed (but not tested) by design and characteri-
zation data.
V
Parameter is a typical value for information purposes only.
VI
100% production tested at TA = +25 °C. Parameter is guaranteed
over specified temperature range.


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