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SPT7725 Datasheet(PDF) 8 Page - Cadeka Microcircuits LLC.

Part # SPT7725
Description  8-BIT, 300 MSPS, FLASH A/D CONVERTER
Download  12 Pages
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Manufacturer  CADEKA [Cadeka Microcircuits LLC.]
Direct Link  http://www.cadeka.com
Logo CADEKA - Cadeka Microcircuits LLC.

SPT7725 Datasheet(HTML) 8 Page - Cadeka Microcircuits LLC.

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8/17/01
SPT7725
OPERATION
The SPT7725 has 256 preamp/comparator pairs that are
each supplied with the voltage from VRTF to VRBF divided
equally by the resistive ladder as shown in the block dia-
gram. This voltage is applied to the positive input of each
preamplifier/comparator pair. An analog input voltage ap-
plied at VIN is connected to the negative inputs of each
preamplifier/comparator pair. The comparators are then
clocked through each comparator’s individual clock buffer.
When CLK pin is in the low state, the master or input stage
of the comparators compares the analog input voltage to
the respective reference voltage. When CLK changes
from low to high, the comparators are latched to the state
prior to the clock transition and output logic codes in
sequence from the top comparators, closest to VRTF (0 V),
down to the point where the magnitude of the input signal
changes sign (thermometer code). The output of each
comparator is then registered into four 64-to-6 bit decod-
ers when CLK is changed from high to low.
At the output of the decoders is a set of four 7-bit latches
that are enabled (
track) when CLK changes from high to
low. From here, the outputs of the latches are coded into
6 LSBs from 4 columns, and 4 columns are coded into
2 MSBs. Next are the MINV and LINV controls for output
inversions, which consist of a set of eight XOR gates.
Finally, 8 ECL output latches and buffers are used to drive
the external loads. The conversion takes one clock cycle
from the input to the data outputs.
Figure 3 – Timing Diagram
tPW1
N
N+2
N+1
N
N–1
tD
Data Output D0–D7
CLK
Analog Input
Clock
VIN
6 Bit Latch Output
8 Bit Latch Output
Master
Slave
CLK
Comparator Output
N+1
Data Ready
Overrange D8
Timing for PGA and Cerquad Packages Only
tPW0


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