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3/11/97

SPT7824

DIGITAL OUTPUTS

The format of the output data (D0-D9) is straight binary. (See

table II.) The outputs are latched on the rising edge of CLK

with a propagation delay of 14 ns (typ). There is a one clock

cycle latency between CLK and the valid output data. (See

timing diagram.)

Table II - Output Data Information

ANALOG INPUT

OVERRANGE

OUTPUT CODE

D1O

D9-DO

>+2.0 V + 1/2 LSB

1

1 1 1111

1111

+2.0 V -1 LSB

O

11 1111

111Ø

0.0 V

O

ØØ ØØØØ ØØØØ

-2.0 V +1 LSB

O

OO OOOO OOOØ

<-2.0 V

O

OO OOOO OOOO

(Ø indicates the flickering bit between logic 0 and 1).

The rise times and fall times of the digital outputs are not

symmetrical. The propagation delay of the rise time is typi-

cally 14 ns and the fall time is typically 6 ns. (See figure 5.)

The nonsymmetrical rise and fall times create approximately

8 ns of invalid data.

OVERRANGE OUTPUT

The OVERRANGE OUTPUT (D10) is an indication that the

analog input signal has exceeded the positive full scale input

voltage by 1 LSB. When this condition occurs, D10 will switch

to logic 1. All other data outputs (D0 to D9) will remain at

logic 1 as long as D10 remains at logic 1. This feature makes

it possible to include the SPT7824 into higher resolution

systems.

EVALUATION BOARD

The EB7824 Evaluation Board is available to aid designers in

demonstrating the full performance of the SPT7824. This

board includes a reference circuit, clock driver circuit, output

data latches and an on-board reconstruction of the digital

data. An application note describing the operation of this

board as well as information on the testing of the SPT7824 is

also available. Contact the factory for price and availability.

Figure 5 - Digital Output Characteristics

3.5 V

N+1

Rise Time

6 nsec

6 ns

typ.

CLK In

N

2.4 V

Invalid

Data

(N-1)

(N-2)

(N-1)

Data Out

(Equivalent)

Invalid

Data

Data Out

(Actual)

(N-2)

(N-1)

(N)

2.4 V

0.8 V

0.5 V

tpd1

(14 ns typ.)

Invalid

Data

Invalid

Data