8

6/15/01

SPT7850

Table II – Clock Cycles

Clock

Operation

1

Reference zero sampling

2

Auto-zero comparison

3

Auto-calibrate comparison

4

Input sample

5-15

11-bit SAR conversion

16

Data transfer

The 16-phase clock, which is derived from the input clock,

synchronizes these events. The timing signals for adjacent

ADC sections are shifted by two clock cycles so that the

analog input is sampled on every other cycle of the input

clock by exactly one ADC section. After 16 clock periods,

the timing cycle repeats. The sample rate for the configu-

ration is one-half of the clock rate; e.g., for a 40 MHz clock

rate, the input sample rate is 20 MHz. The latency from

analog input sample to the corresponding digital output is

12 clock cycles.

• Since only eight comparators are used, a huge power

savings is realized.

• The auto-zero operation is done using a closed loop

system that uses multiple samples of the comparators’

response to a reference zero.

• The auto-calibrate operation, which calibrates the gain

of the MSB reference and the LSB reference, is also

done with a closed loop system. Multiple samples of the

gain error are integrated to produce a calibration volt-

age for each ADC section.

• Capacitive displacement currents, which can induce

sampling error, are minimized since only one compara-

tor samples the input during a clock cycle.

• The total input capacitance is very low since sections of

the converter that are not sampling the signal are iso-

lated from the input by transmission gates.

VOLTAGE REFERENCE

The SPT7850 requires the use of a single external voltage

reference for driving the high side of the reference ladder.

It must be within the range of 3 V to 5 V. The lower side of

the ladder is typically tied to AGND (0.0 V), but can be run

up to 2.0 V with a second reference. The analog input volt-

age range will track the total voltage difference measured

Force and sense taps are provided to ensure accurate

and stable setting of the upper and lower ladder sense line

voltages across part-to-part and temperature variations.

By using the configuration shown in figure 3, offset and

gain errors of less than ±2 LSB can be obtained.

In cases where wider variations in offset and gain can be

force and sense lines to AGND with a .01 µF capacitor

(chip cap preferred) to minimize high-frequency noise in-

jection. If this simplified configuration is used, the following

considerations should be taken into account.

The reference ladder circuit shown in figure 4 is a simpli-

fied representation of the actual reference ladder with

force and sense taps shown. Due to the actual internal

Figure 3 – Ladder Force/Sense Circuit

AGND

+

–

All capacitors are 0.01 µF

+

–

Figure 4 – Reference Ladder

R/2

R

R

R

R

R

R

R/2

R=30 W (typ)

All capacitors are 0.01 µF

(AGND)

0.0 V

(0.075 V)

(+3.91 V)

+4.0 V

External

Reference

75 mV

90 mV